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TMPR3916 Datasheet(PDF) 125 Page - Toshiba Semiconductor

Part # TMPR3916
Description  32-Bit TX System RISC TX39 Family TMPR3916
PDF  225 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR3916 Datasheet(HTML) 125 Page - Toshiba Semiconductor

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Chapter 7 CAN Module (TXCAN)
Preliminary
7-4
7.2.1
Mailbox Structure
The following picture shows the structure of the mailbox RAM:
ID0
ID1
ID2
ID3
TSV1
TSV0
MCF
D0
D1
D2
D3
D7
D6
D5
D4
0
7
8
15
16
24 23
31
ID0
ID1
ID2
ID3
TSV1
TSV0
MCF
D0
D1
D2
D3
D7
D6
D5
D4
Address
0x000
0x004
0x008
0x00C
0x0F0
0x0F4
0x0F8
0x0FC
Mailbox 0
Mailbox 15
Byte 0
Byte 1
Byte 2
Byte 3
Halfword 0
Halfword 1
Word
Figure 7.2.1 Mailbox RAM Structure
Each mailbox consists of 16 bytes. The first 4 bytes ID0 to ID3 contain the identifier. Byte 4 (MCF)
contains the message control field and byte 5 is unused. Byte 6 and 7 are reserved for the time stamp
value TSV of an implemented free running counter that indicates when a message was received or
transmitted. The data field consists of the bytes D0 to D7.
One mailbox includes the following data:
•
29 bit identifier, 11 bit base ID and 18 bit extended ID (ID0-ID3)
•
identifier extension bit (IDE) (ID3, bit 7)
•
global (local) acceptance mask enable bit GAME (LAME) (ID3, bit 6)
•
remote frame handling bit RFH (ID3, bit 5)
•
remote transmission request bit (RTR) (MCF, bit 4)
•
data length code (DLC) (MCF, bit 0-3)
•
up to eight bytes for the data field (D0-D7)
•
two bytes for the time stamp value (TSV)



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