TMPR3916 datasheet(128/225 Pages) TOSHIBA

128 / 225 page

Chapter 7 CAN Module (TXCAN)

Preliminary

7-7

7.2.3

Message Transmission

The transmission control consists of two registers. One register for setting (TRS) and one for

resetting (TRR) the transmission request. In this manner it is possible to clear the transmission request

without generating a conflict in the handling of the transmit mailboxes in the state-machine. This

mechanism also prevents the clearing of the transmission request of a mailbox which transmission is

already in progress.

The data to be transmitted will be stored in a mailbox configured as transmit mailbox (MDn = 0).

After writing the data and the identifier into the mailbox RAM, the message will be sent if the

corresponding TRS bit has been set and the mailbox is enabled (MCn = 1).

If there is more than one mailbox configured as transmission mailbox and more than one

corresponding TRS bit is set, then the messages will be sent in the selected order. The order of

transmission can be selected in the Master Control Register (MCR).

If MTOS is set to “0”, the mailbox with the lower number has the higher priority. For example: if the

mailboxes MB0, MB2 and MB5 are configured for transmission and the corresponding TRS bits are set,

then the messages will be transmitted in the following order: MB0, MB2 and MB5. If a new

transmission request is set for MB0 during the processing of MB2 then in the next internal arbitration-

run MB0 will be selected for the next transmission. This will also happen, when the TXCAN loses

arbitration while transmitting MB2. In this case, MB0 will be sent at the next opportunity instead of

MB2.

If MTOS is set to “1”, the priority of the identifier stored in the mailbox will determine the sending

order. The mailbox with the higher priority identifier will be sent first.

In case of a lost arbitration on the CAN bus line a new internal arbitration run will be started and the

message with the highest priority will be sent at the next possible time.

Transmission Request Set Register (TRS)

Bit

Name



TRS

Bit

Name

Function

Reset

Value

Mode



Wired to zero

14:0

TRS

Setting TRSn causes the particular message “n” to be transmitted.

Several bits can be set simultaneously. The messages will be sent

one after the other in the selected transmission order. The

transmission order can be selected by the MTOS bit in the Master

Control Register (MCR).

The bits in TRS will be set by writing “1” at the corresponding bit

position from the MCU. Writing a “0” has no effect. After power-up,

all bits are cleared.

R/S

The TRS bits can only be set by the MCU and will be reset by internal logic in case of a successful

transmission or an aborted transmission (if requested by setting the corresponding TRR bit) or a

hard/software reset. Bit 15 is not implemented because the mailbox 15 is the receive-only mailbox. If a

mailbox is configured as receive the corresponding bit in TRS can not be set by MCU.

TMPR3916 Datasheet(PDF) 128 Page - Toshiba Semiconductor

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