TMPR3916 datasheet(170/225 Pages) TOSHIBA

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Chapter 9 Synchronous Serial I/O (TXSEI)

Preliminary

9-15

9.3

TXSEI Operations

There are five signals associated with SEI transfers multiplexed on the PIO pins. The use of each signal

depends on the mode (master/slave) of the SEI device. Because the SEI signals are on a shared pin it is

necessary to deactivate PIOs 16, 17, 18, 19 and 22 by writing a zero to bits 16, 17, 18, 19 and 22 in the

PMUX register. Furthermore the selection whether TXSEI or UART0 functionality is mapped to the

corresponding pins has to be done via the Chip Configuration Register (CCR).

A typical configuration consists out of one master device, which controls several slave devices. Only the

master and one slave device are active at once. The master selects one slave for communication using the

PORT pins to select each slave separately. Only the selected slave enables its port driver for the RX signal.

TXSEI offers a dedicated Slave Select input, which allows it to act on busses with multiple master

devices. The dedicated Slave Select input guarantees a fast response to master’s device selection on the bus.

PIO16/CLK(SEI)/CLK(SIO0) pin:

In master mode the CLK pin is used as an output, in slave mode it functions as input. When TXSEI is

configured as master, the CLK signal is derived from the internal TXSEI clock generator depending on

the SEI polarity and clock rate settings. When the master initiates a transfer, a programmable number of

5 to 16 clock cycles are automatically generated on the CLK pin. When TXSEI is configured as a slave,

the CLK pin synchronizes data output and input to and from the external master. In both the master and

slave SEI device, data is shifted on one edge of the CLK signal and is sampled on the opposite edge

where data is stable. The edge polarity is determined by the SEI transfer protocol.

PIO18/TX(SEI)/TX(SIO0) and PIO17/RX(SEI)/RX(SIO1)

The RX and TX data pins are used for receiving and transmitting serial data. When the SEI is

configured as a master, RX is the data input line, and TX is the master data output line. When the SEI is

configured as a slave, these pins reverse roles.

PIO19/SSI(SEI)/CLK(SIO1) pin

The Slave Select Input port is used in Slave mode. The Slave Select Input signal is active low. If

TXSEI’s Slave Select Input is inactive, TXSEI will not follow the transmissions on the SEI bus.

If the Slave Select signal goes inactive during a running transfer and there are still other bits of the

current transfer expected to receive, a Transfer Format Error will be signaled. The current value of the

shift buffer will be transferred to the receive buffer despite of this error.

When TXSEI is configured to be the master and the SSI pin is asserted a transmission error will be

recognized. This function can be disabled with the SSIVAL bit in the SECR0 register.

PIO22/SSO(SEI)/RTS(SIO1) pin

PIO22 is the dedicated slave select output signal and is asserted during transfer in master mode by the

TXSEI device. In the case that the protocol of the connected device expects that the SS signal idles low

for longer than 16 bits this signal must be generated using the PORT module.

TMPR3916 Datasheet(PDF) 170 Page - Toshiba Semiconductor