TMPR3916 datasheet(171/225 Pages) TOSHIBA

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Chapter 9 Synchronous Serial I/O (TXSEI)

Preliminary

9-16

9.3.1

TXSEI Transfer Format

During an SEI transfer, data is simultaneously transmitted (shifted out serially) and received serially

(shifted in serially). The serial clock synchronizes shifting and sampling of the information on the two

serial data lines.

The transfer format depends on the settings of the SPHA and SPOL registers in the SECR0 register.

SPHA switches between two fundamentally different transfer protocols, which are described below.

9.3.1.1

SPHA Equals 0 Format

SCK (SPOL = 0)

SCK (SPOL = 1)

Cycle #

SRRDY

n= 5,6,...,16

n-3

n-2

n-1

Sample Point

Figure 9.3.1 Protocol Timing for SPHA=0

In this transfer format, the bit value is captured on the first clock edge. This will be on a rising

edge when SPOL equals zero and on a falling edge when SPOL equals one. The levels on the TX

and RX signals change with the second clock edge on SCK. This clock edge will be a falling edge

when SPOL equals zero and a rising edge, when SPOL equals one. With SPOL equal to zero, the

shift clock will idle low. With SPOL equals 1 it will idle high.

In master mode, when a transfer is initiated by writing a new value to the SEDR register the

new data is placed on the TX signal for half a clock cycle before the shift clock starts to operate.

After the last shift cycle, the STRDY and SRRDY flags will be asserted.

In this format the SS signal has to be deasserted and reasserted between each successive frame.

If the TXSEI is configured as a slave, SS has to be deasserted at least for the period of one TXSEI

bit time (at least 8 system clocks).

TMPR3916 Datasheet(PDF) 171 Page - Toshiba Semiconductor