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TMPR3916 Datasheet(PDF) 174 Page - Toshiba Semiconductor

Part # TMPR3916
Description  32-Bit TX System RISC TX39 Family TMPR3916
PDF  225 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR3916 Datasheet(HTML) 174 Page - Toshiba Semiconductor

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Chapter 9 Synchronous Serial I/O (TXSEI)
Preliminary
9-19
9.3.2.4
SETF – Transfer Format Error
This error is generated, if the transfer format is violated.
There are two different scenarios, in which a Transfer Format Error could occur.
In slave mode, a transfer format error will be signaled, if:
•
the slave select pin is used for TXSEI purpose (Configured in the port register) and
•
TXSEI is in the middle of a transfer and
•
the number of bits received yet is smaller than the number specified in the SSZ (SECR1)
register
and if the slave select signal is set inactive at this point. It signals the user, that the master ended
the transfer before the expected end of the transfer. A possible cause for this error could be
different transfer length settings for master and slave devices. The partially received value will not
be stored in the receive buffer since it is not complete.
In master mode, a transfer format error will be signaled, if:
•
the slave select input signal is enabled in master mode (SSIVAL bit in SECR0 register) and
•
both the master bit is set to one (MSTR bit in SECR0) and the system is in active mode
(OPMODE=“10” in SEMCR) and
•
the Slave Select signal is asserted.
9.4
Interrupts
TXSEI connects to three interrupt signals.
•
SEIEXC: System Error Flags SEOE, SEUE, SETF, SIDLE (separately maskable)
•
SEIRX
Rx Buffer Fill Level Interrupt, Flag RBSI (not maskable)
•
SEITX
Tx Buffer Fill Level Interrupt, Flag TBSI (not maskable)
Interrupt SEIEXC is used for error detection purpose (SEOE, SEUE, SETF) and idle state interrupt
(SIDLE). The interrupts SEIRX and SEITX are used to fetch and setup new data in an interrupt service
routine for transferring data.
All the interrupts will occur one system clock cycle later than the internal flags, which are visible in the
status register.



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