TMPR3916 datasheet(172/225 Pages) TOSHIBA

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Chapter 9 Synchronous Serial I/O (TXSEI)

Preliminary

9-17

9.3.1.2

SPHA Equals 1 Format

CLK (SPOL = 0)

CLK (SPOL = 1)

Cycle #

n=5,6,...,16

n-3

n-2

n-1

Sample Point

SRRDY

Figure 9.3.2 Protocol Timing for SPHA=1

In this transfer format, the first bit is shifted in on the second clock edge. This will be on a

falling edge when SPOL equals 0 and on a rising edge when SPOL equals 1. If SPOL equals 0, the

shift clock will idle low; with SPOL equals 1 it will idle high.

In master mode, when a transfer is initiated by writing a new value to the SEDR register the

new data is placed on the TX signal with the first edge of the shift clock.

9.3.1.3

Inter-Frame Space Delay Mechanism

Due to its DMA support and its buffered shift register, TXSEI is able to sustain high data rates,

with only a minimum amount of space between two consecutive frames.

However, between consecutive transfers it still has to be ensured that the slave device can keep

up with the transfer rate of the SEI master. If TXSEI is configured as a master, the slave device

typically has to write new values to its transmit buffer, before the next transfer can be started. To

allow this, usually a minimum inter-frame space is specified considering interrupt response and

data fetch time of the slave device.

TXSEI eases the implementation of this inter-frame space by offering an automated mechanism

to guarantee inter-frame delays between consecutive frames.

The inter-frame space counter is implemented as a 10 bit down counter. The counter is reloaded

with the value from the SEFS register after each transfer. The next transfer will not start before the

IFS counter reaches a value of zero. The internal IFS counter is reset every time the SEFS register

is written. Therefore, if the module is in the inter-frame space the next transfer will start

immediately, if the register is written, even if the same value is rewritten to the register.

TMPR3916 Datasheet(PDF) 172 Page - Toshiba Semiconductor