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TMPR3916 Datasheet(PDF) 204 Page - Toshiba Semiconductor |
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TMPR3916 Datasheet(HTML) 204 Page - Toshiba Semiconductor |
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204 / 225 page ![]() Chapter 11 Electrical Characteristics Preliminary 11-5 11.5 Standby Mode Timing To resume the PLL circuit operations, set the PLLOFF* pin to “High” and the CLKEN pin to high. At that time, a period of 500 µs is required for the PLL circuit oscillation to stabilize. The following diagram shows the corresponding timing: SYSCLK CLKEN min 500 µs PLLOFF* PLL oscillation PLLSTOP Figure 11.5.1 Standby Mode Waveform 11.6 Boot Device By using the following application circuit, the user can choose between 16 bit and 32 bit boot device. TMPR3916 A26 Memory Device R = 47 K Ω VCC VSS Jumper Jumper connected to ... VCC => Boot by 16 Bit device VSS => Boot by 32 Bit device Figure 11.6.1 Applying External Boot Mode Selection Circuit |
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