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TMPR3916 Datasheet(PDF) 205 Page - Toshiba Semiconductor |
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TMPR3916 Datasheet(HTML) 205 Page - Toshiba Semiconductor |
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205 / 225 page  Chapter 11 Electrical Characteristics Preliminary 11-6 11.7 SDRAM Timing Designing the SDRAM interface the following guidelines should be considered: • SDRAM signals should be routed using a comparable wire-length for each interface signal • capacitive load mismatches between different interface signals should be avoided For the following electrical specification of the TMPR3916F external bus interface, balanced loads and equal wiring lengths of the interface signals are assumed. A[31:0] BE[3:0] WE RAS, CAS SYSCLK Dout[31:0] write access read access A[31:0] BE[3:0] WE RAS,CAS SYSCLK Din[31:0] tDOS sample point tDOH tDIS tDIH t CR t CF Figure 11.7.1 SDRAM Interface Timing Diagram Parameter Symbol Min Typ Max Unit Output Setup Time tDOS 4.5 ns Output Hold Time tDOH 2.5 ns Input Setup Time tDIS 3,5 ns Input Hold Time tDIH 1.5 ns Clock Rise Time tCR 4.0 ns Clock Fall Time tCF 4.0 ns Load on Interface Signals CIF 30 pF |
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