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TMPR3916 Datasheet(PDF) 206 Page - Toshiba Semiconductor |
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TMPR3916 Datasheet(HTML) 206 Page - Toshiba Semiconductor |
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206 / 225 page  Chapter 11 Electrical Characteristics Preliminary 11-7 11.8 ROM / SRAM Timing SYSCLK CS A BE RD D* tAOD tDIS tDIH tAOH Sample Point Cycle is determined by RWT setting * Driven by the external memory device tAOH Figure 11.8.1 ROM/Flash/SRAM Interface Timing Diagram (Read) SYSCLK CS A BE WR D* tAOD tAOH Write Hold Time is determined by RWT setting * Driven by TMPR3916F tAOH tDOD tDOH tACW Figure 11.8.2 ROM/Flash/SRAM Interface Timing Diagram (Write) Parameter Symbol Min Typ Max Unit Address, Control Output Drive Time tAOD 12 ns Data Output Drive Time tDOD 12,5 ns Address, Control Output Hold Time tAOH 2,0 ns Data Output Hold Time tDOH 2,0 ns Address to CS or WR 1 tACW 0 ns Data Input Setup Time tDIS 3 ns Data Input Hold Time tDIH 2 ns Load on Interface Signals CIF 30 pF 1 Assumes balanced loads on WR, CS and Address pins. |
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