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XC2000 Datasheet(PDF) 29 Page - Infineon Technologies AG |
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XC2000 Datasheet(HTML) 29 Page - Infineon Technologies AG |
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29 / 647 page ![]() XC2000 Derivatives System Units (Vol. 1 of 2) Architectural Overview Preliminary User’s Manual 2-1 V1.0, 2007-06 ArchitectureX2K, V1.0 2 Architectural Overview The architecture of the XC2000 core combines the advantages of both RISC and CISC processors in a very well-balanced way. This computing and controlling power is completed by the DSP-functionality of the MAC-unit. The XC2000 integrates this powerful CPU core with a set of powerful peripheral units into one chip and connects them very efficiently. On-chip memory blocks with dedicated buses and control units store code and data. This combination of features results in a high performance microcontroller, which is the right choice not only for today’s applications, but also for future engineering challenges. One of the buses used concurrently on the XC2000 is the LXBus, an internal representation of the external bus interface. This bus provides a standardized method for integrating additional application-specific peripherals into derivatives of the standard XC2000. Figure 2-1 XC2000 Functional Block Diagram C166SV2 - Core DPRAM 2 Kbytes CPU BRGen ADC 8-Bit/ 10-Bit 8 Ch. USIC0 2 Ch., 64 x Buffer RS232, LIN, SPI, IIC, IIS RTC WDT Inter rupt & PEC EBC LXBus Control External Bus Control DSRAM 16 Kbytes PSRAM 64 Kbytes Oscillators/PLL, System Fct. Clock, Reset, Power Control, Stand-By RAM OCDS Debug Support Interrupt Bus 8 P15 P9 P7 P6 Port 5 P4 P3 P2 P1 P0 8 8 8 13 8 4 5 16 8 MC_XC2X_BLOCKDIAGRAM Program Flash 0 256 Kbytes Program Flash 1 256 Kbytes Program Flash 2 256 Kbytes GPT T6 T5 T4 T3 T2 ADC 8-Bit/ 10-Bit 16 Ch. CC2 T8 T7 Multi CAN 5 ch. USIC2 2 Ch., 64 x Buffer RS232, LIN, SPI, IIC, IIS USIC1 2 Ch., 64 x Buffer RS232, LIN, SPI, IIC, IIS CCU63 T13 T12 CCU60 T13 T12 P8 7 P10 16 P11 6 ... |
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