XC2000 datasheet(53/647 Pages) INFINEON

53 / 647 page

XC2000 Derivatives

System Units (Vol. 1 of 2)

Architectural Overview

Preliminary

User’s Manual

2-25

V1.0, 2007-06

ArchitectureX2K, V1.0

In addition to the FIFO buffer, a bypass mechanism allows the introduction of high-

priority data without flushing the FIFO buffer.

• Transmit control information

For each data word to be transmitted, a 5-bit transmit control information has been

added to automatically control some transmission parameters, such as word length,

frame length, or the slave select control for the SPI protocol. The transmit control

information is generated automatically by analyzing the address where the user SW

has written the data word to be transmitted (32 input locations = 2^5 = 5 bit transmit

control information).

This feature allows individual handling of each data word, e.g. the transmit control

information associated to the data words stored in a transmit FIFO can automatically

modify the slave select outputs to select different communication targets (slave

devices) without CPU load. Alternatively, it can be used to control the frame length.

• Flexible frame length control

The number of bits to be transferred within a data frame is independent of the data

word length and can be handled in two different ways. The first option allows

automatic generation of frames up to 63 bits with a known length. The second option

supports longer frames (even unlimited length) or frames with a dynamically controlled

length.

• Interrupt capability

The events of each USIC channel can be individually routed to one of 4 service

request outputs, depending on the application needs. Furthermore, specific start and

end of frame indications are supported in addition to protocol-specific events.

• Flexible interface routing

Each USIC channel offers the choice between several possible input and output pins

connections for the communications signals. This allows a flexible assignment of

USIC signals to pins that can be changed without resetting the device.

• Input conditioning

Each input signal is handled by a programmable input conditioning stage with

programmable filtering and synchronization capability.

• Baud rate generation

Each USIC channel contains an own baud rate generator. The baud rate generation

can be based either on the internal module clock or on an external frequency input.

This structure allows data transfers with a frequency that can not be generated

internally, e.g. to synchronize several communication partners.

• Transfer trigger capability

In master mode, data transfers can be triggered events generated outside the USIC

module, e.g. at an input pin or a timer unit (transmit data validation). This feature

allows time base related data transmission.

• Debugger support

The USIC offers specific addresses to read out received data without interaction with

the FIFO buffer mechanism. This feature allows debugger accesses without the risk

of a corrupted receive data sequence.

XC2000 Datasheet(PDF) 53 Page - Infineon Technologies AG

XC2000 Datasheet(HTML) 53 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL