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XC2000 Datasheet(PDF) 77 Page - Infineon Technologies AG

Part # XC2000
Description  16/32-Bit Single-Chip Microcontroller with 32-Bit Performance Volume 1 (of 2): Peripheral Units
PDF  647 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

XC2000 Datasheet(HTML) 77 Page - Infineon Technologies AG

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XC2000 Derivatives
System Units (Vol. 1 of 2)
Memory Organization
Preliminary
User’s Manual
3-15
V1.0, 2007-06
MemoryX2K, V1.1
3.6
IO Areas
The following areas of the XC2000’s address space are marked as IO area:
•The external IO area is provided for external peripherals (or memories) and also
comprises the on-chip LXBus-peripherals, such as the CAN or USIC modules. It is
located from 20’0000H to 3F’FFFFH (2 Mbytes).
•The internal IO area provides access to the internal peripherals and is split into three
blocks:
– The SFR area, located from 00’FE00H to 00’FFFFH (512 bytes).
– The ESFR area, located from 00’F000H to 00’F1FFH (512 bytes).
– The XSFR area, located from 00’E000H to 00’EFFFH (4 Kbytes).
Note: The external IO area supports real byte accesses. The internal IO area does not
support real byte transfers, the complementary byte is cleared when writing to a
byte location.
The IO areas have special properties, because peripheral modules must be controlled
in a different way than memories:
•
Accesses are not buffered and cached, the write back buffers and caches are not
used to store IO read and write accesses.
•
Speculative reads are not executed, but delayed until all speculations are solved (e.g.
pre-fetching after conditional branches).
•
Data forwarding is disabled, an IO read access is delayed until all IO writes pending
in the pipeline are executed, because peripherals can change their internal state after
a write access.



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