XC2000 datasheet(97/647 Pages) INFINEON

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XC2000 Derivatives

System Units (Vol. 1 of 2)

Memory Organization

Preliminary

User’s Manual

3-35

V1.0, 2007-06

MemoryX2K, V1.1

3.9.5

Data Integrity

This section describes means for detecting and preventing the inadvertent modification

of data in the flash memory.

3.9.5.1

Error Correcting Codes (ECC)

With very low probability a flash cell can lose its data value faster than specified. In order

to reach the defined overall device reliability each 128-bit block of flash data is

accompanied with a 9-bit ECC value. This redundancy supplies SEC-DED capability,

meaning “single error correction and double error detection”. All single bit errors are

corrected (and the incident is detected), all double bit errors are detected and even most

triple bit errors are detected but some of these escape as valid data or corrected data.

A detected error is reported in the register IMB_FSR_PROT. Software can select which

type of error should trigger a trap by the means of register IMB_INTCTR. In the system

control further means exist to modify the handling of errors (see “SCU Trap Control

Registers” on Page 6-202). The enabled trap requests by the flash module are handled

there as “Flash Access Trap”. In case of a double-bit error the read data is always

replaced with a dummy data word.

3.9.5.2

Aborted Program/Erase Detection

Where the ECC should protect from intrinsic failures of the flash memory that affect

usually only single bits; an interruption of a running program or erase process might

cause massive data corruption:

•

The erase process programs first all cells to 1 before it erases them. So depending

on the time when it is interrupted the data might be in a different state. This can be

the old data, all-one, a random value, a weak all-zero or finally all-zero.

•

The program process programs all bits concurrently from 0 to 1. If it is interrupted not

all set bits might read as 1 or contain a weak 1.

The register IMB_FSR_OP contains the bits ERASE and PROG. These bits stay set until

the next “Clear Status” command or System Reset. So if an erase or program process

is interrupted by an Application Reset one of these bits is still set which allows to detect

the interruption. It lies in the responsibility of the software to send the “Clear Status”

command after a finalized program/erase process to enable this evaluation.

Another possible measure against aborted program/erase processes is to prevent resets

by configuring the SCU appropriately.

3.9.5.3

Read Margins

As explained above interrupting a program or erase process might leave cells in a

weakly erased or programmed state. This is particularly dangerous as following reads

might deliver the correct data with correct ECC but these cells do not have the defined

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