XC2000 datasheet(39/647 Pages) INFINEON

39 / 647 page

XC2000 Derivatives

System Units (Vol. 1 of 2)

Architectural Overview

Preliminary

User’s Manual

2-11

V1.0, 2007-06

ArchitectureX2K, V1.0

read accesses with protected and efficient writing algorithms for programming and

erasing. Dynamic error correction provides extremely high read data security for all read

accesses. Accesses to different Flash modules can be executed in parallel.

Note: Program execution from on-chip program memory is the fastest of all possible

alternatives and results in maximum performance. The type of the on-chip

program memory depends on the chosen derivative. On-chip program memory

also includes the PSRAM.

64 Kbytes of on-chip Program SRAM (PSRAM) are provided to store user code or

data. The PSRAM is accessed via the PMU and is, therefore, optimized for code fetches.

A section of the PSRAM with programmable size can be write-protected.

16 Kbytes of on-chip Data SRAM (DSRAM) are provided as a storage for general user

data. The DSRAM is accessed via a separate interface and is, therefore, optimized for

data accesses.

2 Kbytes of on-chip Dual-Port RAM (DPRAM) are provided as a storage for user

defined variables, for the system stack, and in particular for general purpose register

banks. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide

(RL0, RH0, …, RL7, RH7) so-called General Purpose Registers (GPRs).

The upper 256 bytes of the DPRAM are directly bitaddressable. When used by a GPR,

any location in the DPRAM is bitaddressable.

1 Kbyte of on-chip Stand-By SRAM (SBRAM) is provided as a storage for system-

relevant user data that must be preserved while the major part of the device is powered

down. The SBRAM is accessed via a specific interface and is powered via domain M.

The CPU has an actual register context of up to 16 wordwide and/or bytewide global

GPRs at its disposal, which are physically located within the on-chip RAM area. A

Context Pointer (CP) register determines the base address of the active global register

bank to be accessed by the CPU at a time. The number of register banks is restricted

only by the available internal RAM space. For easy parameter passing, a register bank

may overlap other register banks.

A system stack of up to 32 Kwords is provided as storage for temporary data. The system

stack can be located anywhere within the complete addressing range and it is accessed

by the CPU via the Stack Pointer (SP) register and the Stack Pointer Segment (SPSEG)

stack pointer value upon each stack access for the detection of a stack overflow or

underflow. This mechanism also supports the control of a bigger virtual stack. Maximum

performance for stack operations is achieved by allocating the system stack to internal

data RAM areas (DPRAM, DSRAM).

1) To save control bits, sectors are clustered for protection purposes, they remain separate for programming/

erasing.

XC2000 Datasheet(PDF) 39 Page - Infineon Technologies AG

XC2000 Datasheet(HTML) 39 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL