XC2000 datasheet(60/647 Pages) INFINEON

60 / 647 page

XC2000 Derivatives

System Units (Vol. 1 of 2)

Architectural Overview

Preliminary

User’s Manual

2-32

V1.0, 2007-06

ArchitectureX2K, V1.0

2.4

Clock Generation

The Clock Generation Unit uses a programmable on-chip PLL with multiple prescalers

to generate the clock signals for the XC2000 with high flexibility. The master clock fMC is

the reference clock signal, and is used for TwinCAN and is output to the external system.

The CPU clock fCPU and the system clock fSYS are derived from the master clock either

directly (1:1) or via a 2:1 prescaler (fSYS = fCPU = fMC/2).

The on-chip oscillator can drive an external crystal or accepts an external clock signal.

The oscillator clock frequency can be multiplied by the on-chip PLL (by a programmable

factor) or can be divided by a programmable prescaler factor.

If the bypass mode is used (direct drive or prescaler) the PLL can deliver an independent

clock to monitor the clock signal generated by the on-chip oscillator. This PLL clock is

independent from the XTAL1 clock. When the expected oscillator clock transitions are

missing the Oscillator Watchdog (OWD) activates the PLL Unlock/OWD interrupt node

and supplies the CPU with an emergency clock, the PLL clock signal. Under these

circumstances the PLL will oscillate with its basic frequency.

The oscillator watchdog can be disabled by switching the PLL off. This reduces power

consumption, but also no interrupt request will be generated in case of a missing

oscillator clock.

XC2000 Datasheet(PDF) 60 Page - Infineon Technologies AG