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XC2000 Datasheet(PDF) 23 Page - Infineon Technologies AG

Part # XC2000
Description  16/32-Bit Single-Chip Microcontroller with 32-Bit Performance Volume 1 (of 2): Peripheral Units
PDF  647 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

XC2000 Datasheet(HTML) 23 Page - Infineon Technologies AG

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XC2000 Derivatives
System Units (Vol. 1 of 2)
Introduction
Preliminary
User’s Manual
1-5
V1.0, 2007-06
Intro, V1.0
1.2
Summary of Basic Features
The XC2000 devices are enhanced members of the Infineon family of full featured 16-bit
single-chip CMOS microcontrollers. The XC2000 combines the extended functionality
and performance of the C166SV2 Core with powerful on-chip peripheral subsystems
and on-chip memory units and provides several means for power reduction.
The following key features contribute to the high performance of the XC2000:
High Performance 16-bit CPU with Five-Stage Pipeline and MAC Unit
• Single clock cycle instruction execution
• 1 cycle minimum instruction cycle time (most instructions)
• 1 cycle multiplication (16-bit
× 16-bit
• 4 + 17 cycles division (32-bit / 16-bit), 4 cycles delay, 17 cycles background execution
• 1 cycle multiply and accumulate instruction (MAC) execution
• Automatic saturation or rounding included
• Multiple high bandwidth internal data buses
• Register-based design with multiple, variable register banks
• Two additional fast register banks
• Fast context switching support
• 16 Mbytes of linear address space for code and data (von Neumann architecture)
• System stack cache support with automatic stack overflow/underflow detection
• High performance branch, call, and loop processing
• Zero-cycle jump execution
Control Oriented Instruction Set with High Efficiency
• Bit, byte, and word data types
• Flexible and efficient addressing modes for high code density
• Enhanced boolean bit manipulation with direct addressability of 6 Kbits for peripheral
control and user-defined flags
• Hardware traps to identify exception conditions during runtime
• HLL support for semaphore operations and efficient data access
Power Management Features
• Two IO power domains fulfill system requirements from 3 V to 5 V
• Separately controllable core power domains support wake-up via external triggers or
on-chip timer while drastically reducing the power consumption
• Gated clock concept for improved power consumption and EMC
• Programmable system slowdown via clock generation unit
• Flexible management of peripherals, can be individually disabled
• Programmable frequency output



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