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XC2000 Datasheet(PDF) 78 Page - Infineon Technologies AG

Part # XC2000
Description  16/32-Bit Single-Chip Microcontroller with 32-Bit Performance Volume 1 (of 2): Peripheral Units
PDF  647 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

XC2000 Datasheet(HTML) 78 Page - Infineon Technologies AG

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XC2000 Derivatives
System Units (Vol. 1 of 2)
Memory Organization
Preliminary
User’s Manual
3-16
V1.0, 2007-06
MemoryX2K, V1.1
3.7
External Memory Space
The XC2000 is capable of using an address space of up to 16 Mbytes. Only parts of this
address space are occupied by internal memory areas or are reserved. A total area of
approximately 12 Mbytes references external memory locations. This external memory
is accessed via the XC2000’s external bus interface.
Selectable memory bank sizes are supported: The maximum size of a bank in the
external memory space depends on the number of activated address bits. It can vary
from 64 Kbytes (with A15 … A0 activated) to 12 Mbytes (with A23 … A0 activated). The
logical size of a memory bank and its location in the address space is defined by
programming the respective address window. It can vary from 4 Kbytes to 12 Mbytes.
•
Non-segmented mode:
– 64 Kbytes with A15 … A0 on PORT0 or PORT1.
•
1-bit segmented mode:
– 128 Kbytes with A16 on Port 4
– and A15 … A0 on PORT0 or PORT1.
•
2-bit … 7-bit segmented mode:
– with Ax … A16 on Port 4
– and A15 … A0 on PORT0 or PORT1.
•
8-bit segmented mode:
– 12 Mbytes with A23 … A16 on Port 4
– and A15 … A0 on PORT0 or PORT1.
Each bank can be directly addressed via the address bus, while the programmable chip
select signals can be used to select various memory banks.
The XC2000 also supports four different bus types:
•
Multiplexed 16-bit Bus with address and data on PORT0 (default after Reset).
•
Multiplexed 8-bit Bus with address and data on PORT0/P0L.
•
Demultiplexed 16-bit Bus with address on PORT1 and data on PORT0.
•
Demultiplexed 8-bit Bus with address on PORT1 and data on P0L.
Memory model and bus mode are preselected during reset by pin EA and PORT0 pins.
For further details about the external bus configuration and control please refer to
Chapter XX (The External Bus Controller).
External word and byte data can only be accessed via indirect or long 16-bit addressing
modes using one of the four DPP registers. There is no short addressing mode for
external operands. Any word data access is made to an even byte address.
For PEC data transfers the external memory can be accessed independent of the
contents of the DPP registers via the PEC source and destination pointers.
Note: The external memory is not bit addressable.



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