XC2000 datasheet(33/647 Pages) INFINEON

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XC2000 Derivatives

System Units (Vol. 1 of 2)

Architectural Overview

Preliminary

User’s Manual

2-5

V1.0, 2007-06

ArchitectureX2K, V1.0

2.1.2

Powerful Execution Units

The 16-bit Arithmetic and Logic Unit (ALU) performs all standard (word) arithmetic

and logical operations. Additionally, for byte operations, signals are provided from bits 6

and 7 of the ALU result to set the condition flags correctly. Multiple precision arithmetic

is provided through a ‘CARRY-IN’ signal to the ALU from previously calculated portions

of the desired operation.

Most internal execution blocks have been optimized to perform operations on either 8-bit

or 16-bit quantities. Instructions have been provided as well to allow byte packing in

memory while providing sign extension of bytes for word wide arithmetic operations. The

internal bus structure also allows transfers of bytes or words to or from peripherals based

on the peripheral requirements.

A set of consistent flags is updated automatically in the PSW after each arithmetic,

logical, shift, or movement operation. These flags allow branching on specific conditions.

Support for both signed and unsigned arithmetic is provided through user-specifiable

branch tests. These flags are also preserved automatically by the CPU upon entry into

an interrupt or trap routine.

A 16-bit barrel shifter provides multiple bit shifts in a single cycle. Rotates and arithmetic

shifts are also supported.

The Multiply and Accumulate Unit (MAC) performs extended arithmetic operations

such as 32-bit addition, 32-bit subtraction, and single-cycle 16-bit

× 16-bit multiplication.

The combined MAC operations (multiplication with cumulative addition/subtraction)

represent the major part of the DSP performance of the CPU.

The Address Data Unit (ADU) contains two independent arithmetic units to generate,

calculate, and update addresses for data accesses. The ADU performs the following

major tasks:

• The Standard Address Unit supports linear arithmetic for the short, long, and indirect

addressing modes. It also supports data paging and stack handling.

• The DSP Address Generation Unit contains an additional set of address pointers and

offset registers which are used in conjunction with the CoXXX instructions only.

The CPU provides a lot of powerful addressing modes for word, byte, and bit data

accesses (short, long, indirect). The different addressing modes use different formats

and have different scopes.

Dedicated bit processing instructions provide efficient control and testing of peripherals

while enhancing data manipulation. These instructions provide direct access to two

operands in the bit-addressable space without requiring them to be moved into

temporary flags. Logical instructions allow the user to compare and modify a control bit

for a peripheral in one instruction. Multiple bit shift instructions (single cycle execution)

avoid long instruction streams of single bit shift operations. Bitfield instructions allow the

modification of multiple bits from one operand in a single instruction.

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