XC2000 datasheet(52/647 Pages) INFINEON

52 / 647 page

XC2000 Derivatives

System Units (Vol. 1 of 2)

Architectural Overview

Preliminary

User’s Manual

2-24

V1.0, 2007-06

ArchitectureX2K, V1.0

Universal Serial Interface Channel Modules (USIC)

Each USIC channel can be individually configured to match the application needs, e.g.

the protocol can be selected or changed during run time without the need for a reset. The

following protocols are supported:

• UART (ASC, asynchronous serial channel)

- module capability: receiver/transmitter with max. baud rate fsys/4

- application target baud rate range: 1.2 kBaud to 3.5 MBaud

- number of data bits per data frame 1 to 63

- MSB or LSB first

• LIN Support by HW (low-cost network, baud rate up to 20 kBaud)

- data transfers based on ASC protocol

- baud rate detection possible by built-in capture event of baud rate generator

- checksum generation under SW control for higher flexibility

• SSC/SPI (synchronous serial channel with or without slave select lines)

- module capability: slave mode with max. baud rate fsys

- module capability: master mode with max. baud rate fsys /2

- application target baud rate range: 2 kBaud to 10 MBaud

- number of data bits per data frame 1 to 63, more with explicit stop condition

- MSB or LSB first

• IIC (Inter-IC Bus)

- application baud rate 100 kBaud to 400 kBaud

- 7-bit and 10-bit addressing supported

- full master and slave device capability

• IIS (infotainment audio bus)

- module capability: receiver with max. baud rate fSYS

- module capability: transmitter with max. baud rate fSYS /2

- application target baud rate range: up to 26 MBaud

In addition to the flexible choice of the communication protocol, the USIC structure has

been designed to reduce the system load (CPU load) allowing efficient data handling.

The following aspects have been considered:

• Data buffer capability

The standard buffer capability includes a double word buffer for receive data and a

single word buffer for transmit data. This allows longer CPU reaction times (e.g.

interrupt latency).

• Additional FIFO buffer capability

In addition to the standard buffer capability, the received data and the data to be

transmitted can be buffered in a FIFO buffer structure. The size of the receive and the

transmit FIFO buffer can be programmed independently. Depending on the

application needs, a total buffer capability of 64 data words can be assigned to the

receive and transmit FIFO buffers of a USIC module (the two channels of the USIC

module share the 64 data word buffer).

XC2000 Datasheet(PDF) 52 Page - Infineon Technologies AG

XC2000 Datasheet(HTML) 52 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL