XC2000 datasheet(74/647 Pages) INFINEON

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XC2000 Derivatives

System Units (Vol. 1 of 2)

Memory Organization

Preliminary

User’s Manual

3-12

V1.0, 2007-06

MemoryX2K, V1.1

3.4.1

Program/Data SRAM (PSRAM)

The XC2000 provides 64 Kbytes of PSRAM (E0’0000H … E0’FFFFH). The PSRAM

provides fast code execution without initial delays. Therefore, it supports non-sequential

code execution, for example via the interrupt vector table.

Any word or byte data in the PSRAM can be accessed via indirect or long 16-bit

addressing modes, if the selected DPP register points to one of its data page 896 – 899.

Any word data access is made on an even byte address. The highest possible word data

storage location in the PSRAM is E0’FFFEH.

For PEC data transfers, the PSRAM can be accessed independent of the contents of the

DPP registers via the PEC source and destination pointers.

Any data can be stored in the PSRAM. Because the PSRAM is optimized for code

fetches, however, data accesses to the data memories provide higher performance.

Note: The PSRAM is not bit-addressable.

An area of 512 Kbytes is dedicated to PSRAM (E0’0000H … F7’FFFFH). The locations

without implemented PSRAM are reserved.

Flash Emulation

During code development the PSRAM will often be used for storing code or data that the

production chip will later contain in the flash memory. In order to ensure similar execution

time the PSRAM supports a second access path in the range E8’0000H … EF’FFFFH

with timing parameters that correspond to Flash timing. The number of wait-cycles is

determined by the flash access timing configuration (see IMB_IMBCTRL.WSFLASH).

Writes are always performed without wait-cycles.

This flash access timing imitation is nearly cycle accurate because the same read logic

as for reading the flash memory is used1). Discrepancies might occur if the software uses

the PSRAM for flash emulation and directly as PSRAM. During emulation access

conflicts can cause a slightly different timing as in the product chip where these conflicts

do not occur.

Another source of timing differences can be access conflicts at the flash modules in the

product chip. Data reads and instruction fetches that target different flash modules can

be executed concurrently whereas if they target the same flash module they are

executed sequentially with the data access as first. In the flash emulation this type of

conflict can not occur. The data and the instruction access will both incur the defined

number of wait-cycles (as if they would target different flash modules) and if they collide

at the PSRAM interface the instruction fetch will see an additional wait-cycle.

The dual use of the flash read logic might cause unexpected behavior: while the IMB Core is busy with

updating the protection configuration (after startup or after changing the security pages) read accesses to the

flash emulation range of the PSRAM are blocked because Flash data reads would be blocked also.

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