XC2000 datasheet(90/647 Pages) INFINEON

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XC2000 Derivatives

System Units (Vol. 1 of 2)

Memory Organization

Preliminary

User’s Manual

3-28

V1.0, 2007-06

MemoryX2K, V1.1

not disabled when the “Enter Page Mode” command is received, the command is not

executed, and the protection error flag PROER is set in the IMB_FSR.

Enter Security Page Mode

Arguments: SECPA

Definition:

MOV XXAAH, XX55H

MOV SECPA, XXAAH

Timing: 2-cycle command that sets “BUSY” for around 100 clock cycles.

Description: This command is identical to the “Enter Page Mode” command (see

above), with the following exceptions: The addressed page (SECPA) belongs to the

security pages of the flash memory and not to the user flash range. This command can

only be executed after disabling of read protection and of sector write protection. Only if

protection is not installed (e.g. for the very first installation of keywords), read/write

protection need not be disabled. This command is not accepted and a protection error is

reported if any protection is installed and active.

The use of this command to install passwords and to disable them again is described in

“Protection Handling Details” on Page 3-38.

Load Page Word

Arguments: WD

Definition:

MOV XXF2H, WD

Timing: 1-cycle command that does not set any “BUSY” flags. But note that an

immediately following write access to the IMB Core or read from the flash memory is

stalled for a few clock cycles if it arrives while the IMB Core is busy with copying its block

assembly register content into the flash module assembly buffer. During this stall time

the CPU can not perform any action! So either the user software can accept this stall time

(which must be taken into account for the worst-case interrupt latency) or the software

must avoid the blocking accesses.

Description: Load the IMB Core block assembly register with a 16-bit word and

increment the write pointer. The 128 byte assembly buffer (i.e. a complete page) is filled

by a sequence of 64 “Load Page Word” commands. The word address is not determined

by the command but the “Enter Page Mode” command sets a write word pointer to zero

which is incremented after each “Load Page Word” command.

This (sequential) data write access to the block assembly register belongs to and is only

accepted in Page Mode. The command address of this single cycle command is always

the same (F2H). These low order address bits also identify the “Load Page Word”

command and the sequential write data to be loaded into the block assembly register.

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