XC2000 datasheet(44/647 Pages) INFINEON

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XC2000 Derivatives

System Units (Vol. 1 of 2)

Architectural Overview

Preliminary

User’s Manual

2-16

V1.0, 2007-06

ArchitectureX2K, V1.0

Peripheral Interfaces

The on-chip peripherals generally have two different types of interfaces: an interface to

the CPU and an interface to external hardware. Communication between the CPU and

peripherals is performed through Special Function Registers (SFRs) and interrupts. The

SFRs serve as control/status and data registers for the peripherals. Interrupt requests

are generated by the peripherals based on specific events which occur during their

operation, such as operation complete, error, etc.

To interface with external hardware, specific pins of the parallel ports are used, when an

input or output function has been selected for a peripheral. During this time, the port pins

are controlled either by the peripheral (when used as outputs) or by the external

hardware which controls the peripheral (when used as inputs). This is called the

‘alternate (input or output) function’ of a port pin, in contrast to its function as a general

purpose I/O pin.

Peripheral Timing

Internal operation of the CPU and peripherals is based on the master clock (fMC). The

clock generation unit uses the on-chip oscillator to derive the master clock from the

crystal or from the external clock signal. The clock signal gated to the peripherals is

independent from the clock signal that feeds the CPU. During Idle mode, the CPU’s clock

is stopped while the peripherals continue their operation. Peripheral SFRs may be

accessed by the CPU once per state. When an SFR is written to by software in the same

state where it is also to be modified by the peripheral, the software write operation has

priority. Further details on peripheral timing are included in the specific sections

describing each peripheral.

Programming Hints

• Access to SFRs: All SFRs reside in data page 3 of the memory space. The following

addressing mechanisms allow access to the SFRs:

– Indirect or direct addressing with 16-bit (mem) addresses must guarantee that the

used data page pointer (DPP0 … DPP3) selects data page 3.

– Accesses via the Peripheral Event Controller (PEC) use the SRCPx and DSTPx

pointers instead of the data page pointers.

– Short 8-bit (reg) addresses to the standard SFR area do not use the data page

pointers but directly access the registers within this 512-byte area.

– Short 8-bit (reg) addresses to the extended ESFR area require switching to the

512-byte Extended SFR area. This is done via the EXTension instructions EXTR,

EXTP(R), EXTS(R).

• Byte Write Operations to wordwide SFRs via indirect or direct 16-bit (mem)

addressing or byte transfers via the PEC force zeros in the non-addressed byte. Byte

write operations via short 8-bit (reg) addressing can access only the low byte of an

SFR and force zeros in the high byte. It is therefore recommended, to use the bitfield

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