XC2000 datasheet(85/647 Pages) INFINEON

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XC2000 Derivatives

System Units (Vol. 1 of 2)

Memory Organization

Preliminary

User’s Manual

3-23

V1.0, 2007-06

MemoryX2K, V1.1

3.9.3.2

Data Reads from Flash Memory

Data reads are issued by the DMU. Data is always requested in 16-bit words. The flash

memory delivers for every read request 128 bits plus ECC as described in “Instruction

Fetch from Flash Memory” on Page 3-22.

The IMB Core has to get all 128 bits to evaluate the ECC data. The requested 16 bits will

be delivered to the DMU. All data and ECC bits are kept in the data register and their

address is kept in the address register. For all following data reads the address is

compared with the address register and in case of a match the data is delivered after one

cycle from the data register. Every data read that is not delivered from this cache

invalidates the cache content. When the requested data arrives the cache contains again

valid data.

This small data cache is invalidated when a write (i.e. erase or program) access to this

address happens.

For data reads the IMB Core does not perform any autonomous pre-fetching.

3.9.3.3

Data Writes to Flash Memory

Flash memory content can not be changed by directly writing data to this memory.

Command sequences are used to execute all other operations in the flash except

reading. Command sequences consist of data writes with certain data to the flash

memory address range. All data moves targeting this range are interpreted as command

sequences. If they do not match a defined one or if the IMB Core is busy with executing

a sequence (i.e. it is in “command mode”) a sequence error is reported.

XC2000 Datasheet(PDF) 85 Page - Infineon Technologies AG