XC2000 datasheet(69/647 Pages) INFINEON

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XC2000 Derivatives

System Units (Vol. 1 of 2)

Memory Organization

Preliminary

User’s Manual

3-7

V1.0, 2007-06

MemoryX2K, V1.1

In contrast to the system stack, a register bank grows from lower towards higher address

locations and occupies a maximum space of 32 bytes. The GPRs are accessed via short

2-, 4-, or 8-bit addressing modes using the Context Pointer (CP) register as base

address for the global bank (independent of the current DPP register contents).

Additionally, each bit in the currently active register bank can be accessed individually.

The XC2000 supports fast register bank (context) switching. Multiple global register

banks can physically exist within the DPRAM at the same time. Only the global register

bank selected by the Context Pointer register (CP) is active at a given time, however.

Selecting a new active global register bank is simply done by updating the CP register.

A particular Switch Context (SCXT) instruction performs register bank switching by

automatically saving the previous context and loading the new context. The number of

implemented register banks (arbitrary sizes) is limited only by the size of the available

DPRAM.

Note: The local GPR banks are not memory mapped and the GPRs cannot be accessed

using a long or indirect memory address.

Table 3-2

Mapping of General Purpose Registers to DPRAM Addresses

DPRAM Address High Byte Registers Low Byte Registers

Word Registers

<CP> + 1EH

––R15

<CP> + 1CH

––R14

<CP> + 1AH

––R13

<CP> + 18H

––R12

<CP> + 16H

––R11

<CP> + 14H

––R10

<CP> + 12H

––R9

<CP> + 10H

––R8

<CP> + 0EH

RH7

RL7

<CP> + 0CH

RH6

RL6

<CP> + 0AH

RH5

RL5

<CP> + 08H

RH4

RL4

<CP> + 06H

RH3

RL3

<CP> + 04H

RH2

RL2

<CP> + 02H

RH1

RL1

<CP> + 00H

RH0

RL0

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