XC2000 datasheet(75/647 Pages) INFINEON

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XC2000 Derivatives

System Units (Vol. 1 of 2)

Memory Organization

Preliminary

User’s Manual

3-13

V1.0, 2007-06

MemoryX2K, V1.1

Data Integrity

The PSRAM contains its own parity generation and comparison logic. It generates the

parity bits for every written byte. When reading data it checks the data integrity by

comparing the read parity bits with calculated parity bits.

If enabled parity errors can trigger a trap (see “Memory Parity Error Handling” on

Page 3-77).

Write Protection

As the PSRAM is often used to store timing critical code or constant data it is supplied

with a write protection. After storing critical data in the PSRAM the register field

IMB_IMBCTRH.PSPROT can be used to split the PSRAM into a read-only and a

writable part. Write accesses to the read-only part are blocked and a trap can be

activated.

3.4.2

Non-Volatile Program Memory (Flash)

The XC2000 provides 764 Kbytes of program Flash (C0’0000H … CB’FFFFH). Code and

data fetches are always 64-bit aligned, using byte select lines for word and byte data.

Any word or byte data in the program memory can be accessed via indirect or long 16-

bit addressing modes, if the selected DPP register points to one of the respective data

pages. Any word data access is made on an even byte address. The highest possible

word data storage location in the program memory is CB’FFFEH.

For PEC data transfers, the program memory can be accessed independent of the

contents of the DPP registers via the PEC source and destination pointers.

Note: The program memory is not bit-addressable.

An area of 2 Mbytes is dedicated to program memory (C0’0000H … DF’FFFFH). The

locations without implemented program memory are reserved.

A more detailed description can be found in “Embedded Flash Memory” on

Page 3-18.

XC2000 Datasheet(PDF) 75 Page - Infineon Technologies AG