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XC2000 Datasheet(PDF) 101 Page - Infineon Technologies AG

Part # XC2000
Description  16/32-Bit Single-Chip Microcontroller with 32-Bit Performance Volume 1 (of 2): Peripheral Units
PDF  647 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

XC2000 Datasheet(HTML) 101 Page - Infineon Technologies AG

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XC2000 Derivatives
System Units (Vol. 1 of 2)
Memory Organization
Preliminary
User’s Manual
3-39
V1.0, 2007-06
MemoryX2K, V1.1
3.9.6.1
The Lower Layer “Physical State”
After reset the protection state of the device is restored from the following information:
•
The security page 1 contains a “lock code”. This consists of two words of data (32
bits). If it has the value AA55AA55H then security page 0 determines the protection
state. Otherwise (i.e. the lock code was not found) the device is in the “non-protected
state”. The content of the security page 0 is still copied into the registers as described
in “The Middle Layer “Flash State”” on Page 3-39 but their values are ignored in
the non-protected state.
•
The security page 0 contains the RPRO double bit, the write protection bits SnU and
4 passwords. If the field RPRO contains a valid 01B or 10B entry the page is valid and
the device is in the “protection installed state”. The page content determines the
security settings after startup. If SecP0 contains an invalid RPRO entry the device is
in the “errored protection” state.
To summarize: the content of the security pages determines if the device is in the “non-
protected state”, “protection installed state” or “errored protection state”. These states
are reflected in the register settings of the next layer.
The device is usually delivered in the “non-protected state”.
The exact layout of the security pages is described in “Layout of the Security Pages”
on Page 3-43.
3.9.6.2
The Middle Layer “Flash State”
The middle layer consists of the registers IMB_PROCONx and IMB_FSRx and
commands that manipulate them and the content of the security pages.
During startup the physical state is examined by the IMB Core and it is reflected in the
following bit settings:
•
“non-protected state”: IMB_FSR.PROIN = 0, IMB_FSR.PROINER = 0.
•
“protection installed state”: IMB_FSR.PROIN = 1, IMB_FSR.PROINER = 0.
•
“errored protection state”: IMB_FSR.PROIN = 0, IMB_FSR.PROINER = 1.
The fourth possible setting PROIN=1 and PROINER=1 is invalid and can not occur.
The IMB_PROCONx registers are initialized during startup with the content of the
security page 0. The bits DSBER and DDBER indicate if an ECC error occurred. The
customer software has thus the possibility to detect disturbed security pages and it can
refresh their content.
Commands
Other bits of the IMB_FSR: RPRODIS, WPRODIS, PROER can be manipulated with
command sequences and define together with the other bits the protection effective for
the next layer. All three bits are 0 after system startup.



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