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82G33 Datasheet(PDF) 224 Page - Intel Corporation |
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82G33 Datasheet(HTML) 224 Page - Intel Corporation |
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224 / 437 page ![]() PCI Express* Registers (D1:F0) 224 Datasheet 6.1.49 PVCCAP2—Port VC Capability Register 2 B/D/F/Type: 0/1/0/MMR Address Offset: 108–10Bh Default Value: 00000000h Access: RO Size: 32 bits This register describes the configuration of PCI Express Virtual Channels associated with this port. Bit Access & Default Description 31:24 RO 00h VC Arbitration Table Offset (VCATO): This field indicates the location of the VC Arbitration Table. This field contains the zero-based offset of the table in DQWORDS (16 bytes) from the base address of the Virtual Channel Capability Structure. A value of 0 indicates that the table is not present (due to fixed VC priority). 23:8 RO 0000h Reserved 7:0 RO 00h Reserved 6.1.50 PVCCTL—Port VC Control B/D/F/Type: 0/1/0/MMR Address Offset: 10C–10Dh Default Value: 0000h Access: RO, RW Size: 16 bits Bit Access & Default Description 15:4 RO 000h Reserved 3:1 RW 000b VC Arbitration Select (VCAS): This field will be programmed by software to the only possible value as indicated in the VC Arbitration Capability field. Since there is no other VC supported than the default, this field is reserved. 0 RO 0b Reserved |
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