82G33 datasheet(228/437 Pages) INTEL

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PCI Express* Registers (D1:F0)

228

Datasheet

6.1.54

RCLDECH—Root Complex Link Declaration Enhanced

B/D/F/Type:

0/1/0/MMR

Address Offset:

140–143h

Default Value:

00010005h

Access:

Size:

32 bits

This capability declares links from this element (PEG) to other elements of the root

complex component to which it belongs. See PCI Express specification for

link/topology declaration requirements.

Bit

Access &

Default

Description

31:20

000h

Pointer to Next Capability (PNC): This is the last capability in the

PCI Express extended capabilities list

19:16

Link Declaration Capability Version (LDCV): Hardwired to 1 to

indicate compliances with the 1.1 version of the PCI Express

specification.

15:0

0005h

Extended Capability ID (ECID): Value of 0005h identifies this linked

list item (capability structure) as being for PCI Express Link Declaration

Capability.

6.1.55

ESD—Element Self Description

B/D/F/Type:

0/1/0/MMR

Address Offset:

144–147h

Default Value:

02000100h

Access:

RO, RWO

Size:

32 bits

This register provides information about the root complex element containing this Link

Declaration Capability.

Bit

Access &

Default

Description

31:24

02h

Port Number (PN): This field specifies the port number associated

with this element with respect to the component that contains this

element. This port number value is utilized by the Express port of the

component to provide arbitration to this Root Complex Element.

23:16

RWO

00h

Component ID (CID): This field identifies the physical component

that contains this Root Complex Element.

15:8

01h

Number of Link Entries (NLE): This field indicates the number of

link entries following the Element Self Description. This field reports 1

(to Express port only as we don't report any peer-to-peer capabilities

in our topology).

7:4

Reserved

3:0

Element Type (ET): This field indicates the type of the Root Complex

Element. Value of 0h represents a root port.

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