82G33 datasheet(229/437 Pages) INTEL

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PCI Express* Registers (D1:F0)

Datasheet

229

6.1.56

LE1D—Link Entry 1 Description

B/D/F/Type:

0/1/0/MMR

Address Offset:

150–153h

Default Value:

00000000h

Access:

RO, RWO

Size:

32 bits

This register provides the first part of a Link Entry which declares an internal link to

another Root Complex Element.

Bit

Access &

Default

Description

31:24

00h

Target Port Number (TPN): This field specifies the port number

associated with the element targeted by this link entry (Express Port).

The target port number is with respect to the component that contains

this element as specified by the target component ID.

23:16

RWO

00h

Target Component ID (TCID): This field identifies the physical or

logical component that is targeted by this link entry.

15:2

0000h

Reserved

Link Type (LTYP): This field indicates that the link points to memory-

mapped space (for RCRB). The link address specifies the 64-bit base

address of the target RCRB.

RWO

Link Valid (LV):

0 = Link Entry is not valid and will be ignored.

1 = Link Entry specifies a valid link.

6.1.57

LE1A—Link Entry 1 Address

B/D/F/Type:

0/1/0/MMR

Address Offset:

158–15Fh

Default Value:

0000000000000000h

Access:

RO, RWO

Size:

64 bits

This register provides the second part of a Link Entry which declares an internal link to

another Root Complex Element.

Bit

Access &

Default

Description

63:32

00000000h

Reserved

31:12

RWO

00000h

Link Address (LA): This field contains the memory-mapped base

address of the RCRB that is the target element (Express Port) for this

link entry.

11:0

000h

Reserved

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