82G33 datasheet(232/437 Pages) INTEL

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Direct Memory Interface (DMI) Registers

232

Datasheet

Direct Memory Interface (DMI)

Registers

This Root Complex Register Block (RCRB) controls the (G)MCH-ICH9 serial

interconnect. The base address of this space is programmed in DMIBAR in D0:F0

configuration space. Table 7-1 provides an address map of the DMI registers listed by

address offset in ascending order. Section 7.1 provides register bit descriptions.

Table 7-1. DMI Register Address Map

Address

Offset

Symbol

Default

Value

Access

00–03h

DMIVCECH

DMI Virtual Channel Enhanced

Capability

04010002h

04–07h

DMIPVCCAP1

DMI Port VC Capability Register 1

00000001h

RWO, RO

08–0Bh

DMIPVCCAP2

DMI Port VC Capability Register 2

00000000h

0C–0Dh

DMIPVCCTL

DMI Port VC Control

0000h

RO, RW

10–13h

DMIVC0RCAP

DMI VC0 Resource Capability

00000001h

14–17h

DMIVC0RCTL0

DMI VC0 Resource Control

800000FFh

RO, RW

1A–1Bh

DMIVC0RSTS

DMI VC0 Resource Status

0002h

1C–1Fh

DMIVC1RCAP

DMI VC1 Resource Capability

00008001h

20–23h

DMIVC1RCTL1

DMI VC1 Resource Control

01000000h

RW, RO

26–27h

DMIVC1RSTS

DMI VC1 Resource Status

0002h

84–87h

DMILCAP

DMI Link Capabilities

00012C41h

RO, RWO

88–89h

DMILCTL

DMI Link Control

0000h

RW, RO

8A–8Bh

DMILSTS

DMI Link Status

0001h

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