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82G33 Datasheet(PDF) 234 Page - Intel Corporation |
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82G33 Datasheet(HTML) 234 Page - Intel Corporation |
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234 / 437 page ![]() Direct Memory Interface (DMI) Registers 234 Datasheet 7.1.2 DMIPVCCAP1—DMI Port VC Capability Register 1 B/D/F/Type: 0/0/0/DMIBAR Address Offset: 04–07h Default Value: 00000001h Access: RWO, RO Size: 32 bits This register describes the configuration of PCI Express Virtual Channels associated with this port. Bit Access & Default Description 31:7 RO 0000000h Reserved 6:4 RO 000b Low Priority Extended VC Count (LPEVCC): This field indicates the number of (extended) Virtual Channels in addition to the default VC belonging to the low-priority VC (LPVC) group that has the lowest priority with respect to other VC resources in a strict-priority VC Arbitration. The value of 0 in this field implies strict VC arbitration. 3 RO 0b Reserved 2:0 RWO 001b Extended VC Count (EVCC): This field indicates the number of (extended) Virtual Channels in addition to the default VC supported by the device. The Private Virtual Channel is not included in this count. 7.1.3 DMIPVCCAP2—DMI Port VC Capability Register 2 B/D/F/Type: 0/0/0/DMIBAR Address Offset: 08–0Bh Default Value: 00000000h Access: RO Size: 32 bits This register describes the configuration of PCI Express Virtual Channels associated with this port. Bit Access & Default Description 31:0 RO 00000000h Reserved |
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