82G33 datasheet(230/437 Pages) INTEL

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PCI Express* Registers (D1:F0)

230

Datasheet

6.1.58

PEGSSTS—PCI Express*-G Sequence Status

B/D/F/Type:

0/1/0/MMR

Address Offset:

218–21Fh

Default Value:

0000000000000FFFh

Access:

Size:

64 bits

This register provides PCI Express status reporting that is required by the PCI Express

specification.

Bit

Access &

Default

Description

63:60

Reserved

59:48

000h

Next Transmit Sequence Number (NTSN): This field indicates the

value of the NXT_TRANS_SEQ counter. This counter represents the

transmit Sequence number to be applied to the next TLP to be

transmitted onto the Link for the first time.

47:44

Reserved

43:32

000h

Next Packet Sequence Number (NPSN): This field indicates the

packet sequence number to be applied to the next TLP to be

transmitted or re-transmitted onto the Link.

31:28

Reserved

27:16

000h

Next Receive Sequence Number (NRSN): This field is the

sequence number associated with the TLP that is expected to be

received next.

15:12

Reserved

11:0

FFFh

Last Acknowledged Sequence Number (LASN): This field is the

sequence number associated with the last acknowledged TLP.

82G33 Datasheet(PDF) 230 Page - Intel Corporation

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