82G33 datasheet(427/437 Pages) INTEL

427 / 437 page

Testability

Datasheet

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The above figure shows the wave forms to be able to boot the part into XOR mode.

The straps that need to be controlled during this boot process are BSEL[2:0],

SDVO_CTRLDATA, EXP_EM, EXP_SLR, and XORTEST.

On Broadwater platforms, all strap values must be driven before PWROK asserts.

BSEL0 must be a 1. BSEL[2:1] need to be defined values, but logic value in any order

will do. XORTEST must be driven to 0.

If SDVO is present in the design, SDVO_CTRLDATA must be pulled to logic 1.

Depending on if Static Lane Reversal is used and if the SDVO/PCI Express Coexistence

is selected, EXP_SLR and EXP_EN must be pulled in a valid manner.

Because of the different functionalities of the SDVO/PCI Express interface, not all of

the pins will be used in all implementations. Due to the need to minimize test points

and unnecessary routing, the XOR Chain 14 is dynamic depending on the values of

SDVO_CTRLDATA, EXP_SLR, and EXP_EN. See Table 14-1 for what parts of XOR Chain

14 become valid XOR inputs depending on the use of SDVO_CTRLDATA, EXP_SLR, and

EXP_EN.

Table 14-1. XOR Chain 14 functionality

SDVO_CTRLDATA

EXP_EN

EXP_SLR

XOR Chain 14

EXP_RXP[15:0]

EXP_RXN[15:0]

EXP_TXP[15:0]

EXP_TXN[15:0]

EXP_RXP[15:0]

EXP_RXN[15:0]

EXP_TXP[15:0]

EXP_TXN[15:0]

EXP_RXP[15:8]

EXP_RXN[15:8]

EXP_TXP[15:8]

EXP_TXN[15:8]

EXP_RXP[7:0]

EXP_RXN[7:0]

EXP_TXP[7:0]

EXP_TXN[7:0]

EXP_RXP[15:0]

EXP_RXN[15:0]

EXP_TXP[15:0]

EXP_TXN[15:0]

EXP_RXP[15:0]

EXP_RXN[15:0]

EXP_TXP[15:0]

EXP_TXN[15:0]

82G33 Datasheet(PDF) 427 Page - Intel Corporation

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