TUSB7320 datasheet(102/115 Pages) TI1

102 / 115 page

TUSB7320, TUSB7340

SLLSE76J – MARCH 2011 – REVISED MAY 2012

www.ti.com

9.2

External clock

When using an external clock source, the reference clock should have a ±100 PPM or better frequency

stability and have less than 50-ps absolute peak to peak jitter or less than 25-ps peak to peak jitter after

applying the USB 3.0 jitter transfer function. XI should be tied to the clock source and XO should be left

floating. The input clock must be 1.8-V LVCMOS; this input is not 3.3-V tolerant.

Table 9-1. Input Clock Specification

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

Frequency Tolerance

Operational Temperature

±50

ppm

Frequency Stability

1 year aging

±100

ppm

Rise / Fall Time

20% - 80%

Reference Clock RJ with

0.8

JTF (1 sigma)(1)(2)

Reference Clock TJ with

JTF (total p-p)(2)(3)

Reference Clock Jitter

(absolute p-p)(4)

(1)

Sigma value assuming Gaussian distribution.

(2)

After application of JTF.

(3)

Calculated as 14.1 x RJ+DJ

(4)

Absolute phase jitter (p-p)

Table 9-2. Input Clock 1.8-V DC Characteristics

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

VIH

High-level input voltage

0.65 VDDS

VIL

Low-level input voltage

0.35 VDDS

IO = -2 mA, VDDS = 1.62 to 1.98 V,

VDDS-0.45

driver enabled, pullup or pulldown disabled

VOH

IO = -2 mA, VDDS = 1.4 to 1.6 V,

0.75 VDDS

driver enabled, pullup or pulldown disabled

IO = 2 mA, driver enabled, VDDS = 1.62 to 1.98 V,

0.45

pullup or pulldown disabled

VOL

IO = 2 mA, VDDS = 1.4 to 1.6 V,

0.25 VDDS

driver enabled, pullup or pulldown disabled

9.3

External crystal

An external 2-M

Ω feedback resistor is required between XI and XO when using a crystal. See the table

below for additional crystal specifications.

Table 9-3. Crystal Specification

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

Frequency Tolerance

Operational Temperature

±50

ppm

Frequency Stability

1 year aging

±100

ppm

Load Capacitance

ESR

102

INPUT CLOCK

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Product Folder Link(s): TUSB7320 TUSB7340

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