TUSB7320 datasheet(104/115 Pages) TI1

104 / 115 page

TUSB7320, TUSB7340

SLLSE76J – MARCH 2011 – REVISED MAY 2012

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10.4 Power Management Event (PME)

Power Management Events are generated by Functions as a means of requesting a PM state change.

Power Management Events are typically utilized to revive the system or an individual Function from a low

power state.

Before using any wakeup mechanism, a Function must be enabled by software to do so by setting the

PME_EN bit in the PMCSR, see Section 4.25. The PME_Status bit is sticky, and the value of the

PME_Status bit is maintained through reset if aux power is available and the device is enabled for wakeup

events. The TUSB73x0 needs a clock at all times in order to support wake from system suspend.

10.4.1 PME Support

The 5-bit PME_support field in the PMC (Power Management Capabilities) register, Section 4.24,

indicates the power states in which the TUSB73X0 may send a PME Message. A value of 0b for any bit

indicates that it is not capable of sending PME Message while in that power state. Note that the default

value of the Bit15 of the PME_support for D3cold is "HwInit" and depends on the AUX_DET pin strapping.

If the AUX_DET is pulled high, bit 15 set to 1b.

Table 10-3. PME Support

Pin Name

Support Wake from D3cold/D3hot

Support Wake from D3hot only

3.3V

Power rails must be maintained to support D3cold and

Power rails must be maintained to support D3hot states,

1.1V

D3hot states.

but may be removed for D3cold.

Pulled high.When AUXDET is pulled high, bit 15 of the

Pulled low. When AUXDET is pulled low, bit 15 of the

AUX_DET

Power Management Capabilities register is set to 1b.

Power Management Capabilities register is cleared, or 0b.

Must not be asserted during D3cold and D3hot states

Must not be asserted during D3hot state, but should assert

GRST#

for WAKE# to function correctly. Should be asserted if

if power rails fall below specified operating conditions.

power rails fall below specified operating conditions.

Connected to WAKE# of the system chipset and is

pulled high on the system board. WAKE# is used for

WAKE# is not used. In band PME message is used for

WAKE#

wakeup from D3cold. In band PME message is used

wakeup from D3hot. Should not be pulled high if power is

for wakeup from D3hot. Should not be pulled high if

removed.

power is removed.

Connected to CLKREQ# of the system chipset and is

CLKREQ#

pulled high. Should not be pulled high if power is

pulled high. Should not be pulled high if power is removed.

removed.

Must remain pulled high during D3cold and D3hot

Must remain pulled high during D3hot state. Should not be

OVERCUR(X:1)#

states. Should not be pulled high if power is removed.

pulled high if power is removed.

If an EEPROM is used for configuration, power should also be maintained during D3cold and D3hot

states.

The assertion of PERST# transitions the TUSB7340 from D3hot to D3cold. PERST# must be asserted if

the power rails fall below the specified operation conditions.

The TUSB73x0 will support wake from system suspend if the following conditions are met:

1. TUSB73x0 clock source must never be removed.

2. TUSB73x0 AUX_DET must be pulled to TUSB73x0 VDD33.

3. TUSB73x0 must remain powered in system suspend states.

4. PERST# must be asserted in system suspend states to signal WAKE#.

5. BIOS/OS must set TUSB73x0 PME_ENABLE# prior to system suspend.

6. TUSB73x0 GRST# should never be asserted during system suspend.

7. TUSB73x0 WAKE# pin should be pulled-up and connected to PCIe WAKE# signal.

8. A .001-µF capacitor (to ground) should be placed on TUSB73x0 WAKE# pin.

9. VBUS must remain powered during system suspend states.

104

PCI EXPRESS POWER MANAGEMENT

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