C508 datasheet(46/93 Pages) INFINEON

46 / 93 page

C508

Data Sheet

2000-08

10-Bit A/D Converter

The C508 provides an A/D converter with the following features:

• 8 input channels (Port 4) which can also be used as digital inputs

• 10-bit resolution

• Single or continuous conversion mode

• Interrupt request generation after each conversion

• Using successive approximation conversion technique via a capacitor array

• Built-in hidden calibration of offset and linearity errors

A/D Converter Clock Selection

The ADC uses two clock signals for operation: the conversion clock

fADC (= 1/tADC) and

the input clock

fIN (= 1/tIN). fADC is derived from the C508 system clock 2 × fOSC which

is twice the crystal frequency applied at the XTAL pins via the ADC clock prescaler as

shown in Figure 19. The input clock

fIN is equal to 2 × fOSC. The conversion clock fADC

is limited to a maximum frequency of 2 MHz. Therefore, the ADC clock prescaler must

be programmed to a value which assures that the conversion clock does not exceed 2

MHz. The prescaler ratio is selected by the bits ADCL1 and ADCL0 of SFR ADCON1.

Figure 19

A/D Converter Clock Selection

MUX

÷ 4

÷ 8

÷ 16

÷ 32

Conversion Clock

ADC

A/D

Converter

OSC

ADCL0

ADCL1

ADC max = 2 MHz

Condition:

IN = 2fOSC = 4 TCL

ADC

[MHz]

MCB04102

Oscillator Clock

Rate (

OSC)

[MHz]

Prescaller

Ratio

5 MHz

8 MHz

10 MHz

ADCL1

ADCL0

÷ 8

÷ 16

1.25

Input Clock

1) Note: Please refer to AC characteristics in this document for the definition of TCL.

C508 Datasheet(PDF) 46 Page - Infineon Technologies AG

C508 Datasheet(HTML) 46 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93

Datasheet Download

Link URL