C508 datasheet(60/93 Pages) INFINEON

60 / 93 page

C508

Data Sheet

2000-08

Table 13

Power Saving Modes Overview

Mode

Entering 2-Instruction

Example

Leaving by

Remarks

Idle

Mode

ORL PCON,#01H

ORL PCON,#20H

Occurance of any enabled

interrupt

CPU clock is stopped;

CPU maintains its data;

peripheral units are

active (if enabled) and

provided with clock

Hardware Reset

Slow

Down

Mode

In normal mode:

ORL PCON,#10H

ANL PCON,#0EFH or

Hardware Reset

Internal clock rate is

reduced to a factor of

32 of the nominal

system clock rate (1/16 of

fOSC)

With idle mode:

ORL PCON,#01H

ORL PCON,#30H

Occurance of any enabled

interrupt to exit idle mode

and the instruction

ANL PCON,#0EFH

to terminate slow down

mode

CPU clock is stopped;

CPU maintains all its

data;

Peripheral units are

active (if enabled) and

provided with 1/32 of the

nominal system clock

rate (1/16 of fOSC)

Hardware Reset

Software

Power

Down

mode

With external wake-up

capability from power down

enabled

ORL SYSCON,#10H

ORL PCON1,#80H

(to wake-up via pin P3.2/INT0)

ORL PCON1,#90H

(to wake-up via pin P5.7/INT7)

ANL SYSCON,#0EFH

ORL PCON,#02H

ORL PCON,#40H

Hardware Reset

Oscillator is stopped;

Contents of on-chip

RAM and SFR’s are

maintained

When P3.2/INT0 (or P5.7/

INT7) goes low for at least

µs (latch phase).

But it is desired that the

corresponding pin must be

held at high level during

the power down mode

entry and up to the

wake-up.

With external wake-up

capability from power down

disabled

ORL PCON,#02H

ORL PCON,#40H

Hardware Reset

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