C508 datasheet(80/93 Pages) INFINEON

80 / 93 page

C508

Data Sheet

2000-08

External Data Memory Characteristics

RD pulse width

tRLRH CC 120

–

6 TCL – 30 –

WR pulse width

tWLWH CC 120

–

6 TCL – 30 –

Address hold after ALE

tLLAX2 CC 35

–

2 TCL –15 –

RD to valid data in

tRLDV SR –

–

5 TCL – 50 ns

Data hold after RD

tRHDX SR 0

–

Data float after RD

tRHDZ SR –

–

2 TCL – 12 ns

ALE to valid data in

tLLDV SR –

150

–

8 TCL – 50 ns

Address to valid data in

tAVDV SR –

150

–

9 TCL – 75 ns

ALE to WR or RD

tLLWL CC 60

3 TCL – 15 3 TCL + 15 ns

Address valid to WR

tAVWL CC 70

–

4 TCL – 30 –

WR or RD high to ALE high

tWHLH CC 10

TCL –15

TCL + 15

Data valid to WR transition

tQVWX CC 5

–

TCL – 20

–

Data setup before WR

tQVWH CC 125

–

7 TCL – 50 –

Data hold after WR

tWHQX CC 5

–

TCL – 20

–

Address float after RD

tRLAZ CC –

–

1) Interfacing the C508 to devices with float times up to 20 ns is permissible. This limited bus contention will not

cause any damage to port 0 drivers.

AC Characteristics (cont’d)

(Operating conditions apply)

(

CL for Port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)

Parameter

Symbol

Limit Values

Unit

10-MHz

clock

Duty Cycle

0.5 to 0.5

Variable Clock

4TCL = 5 MHz to

10 MHz

min.

max.

min.

max.

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