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ADSP-BF705BBCZ-4 Datasheet(PDF) 71 Page - Analog Devices |
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ADSP-BF705BBCZ-4 Datasheet(HTML) 71 Page - Analog Devices |
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71 / 116 page  Rev. A | Page 71 of 116 | September 2015 ADSP-BF700/701/702/703/704/705/706/707 DDR2 SDRAM Read Cycle Timing Table 40 and Figure 18 show DDR2 SDRAM read cycle timing, related to the dynamic memory controller (DMC). Table 40. DDR2 SDRAM Read Cycle Timing, VDD_DMC Nominal 1.8 V 200 MHz1 1 To ensure proper operation of the DDR2, all the DDR2 guidelines have to be strictly followed. Parameter Min Max Unit Timing Requirements tDQSQ DMC0_DQS-DMC0_DQ Skew for DMC0_DQS and Associated DMC0_ DQ Signals 0.35 ns tQH DMC0_DQ, DMC0_DQS Output Hold Time From DMC0_DQS 1.8 ns tRPRE Read Preamble 0.9 tCK tRPST Read Postamble 0.4 tCK Figure 18. DDR2 SDRAM Controller Input AC Timing DMC0_CKx DMC0_DQSn tRPRE tDQSQ tDQSQ tQH tRPST DMC0_DQx DMC0_CKx DMC0_DQSn tQH DMC0_Ax DMC0 CONTROL |
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