ADSP-BF705BBCZ-4 datasheet(78/116 Pages) AD

78 / 116 page

Rev. A

Page 78 of 116

September 2015

ADSP-BF700/701/702/703/704/705/706/707

Debug Interface (JTAG Emulation Port) Timing

Table 48 and Figure 26 provide I/O timing, related to the debug interface (JTAG emulator port).

Table 48. JTAG Port Timing

Parameter

VDD_EXT

1.8V Nominal

VDD_EXT

3.3V Nominal

Min

Max

Min

Max

Unit

Timing Requirements

tTCK

JTG_TCK Period

tSTAP

JTG_TDI, JTG_TMS Setup Before JTG_TCK High

tHTAP

JTG_TDI, JTG_TMS Hold After JTG_TCK High

tSSYS

System Inputs Setup Before JTG_TCK High1

1 System inputs = DMC0_DQxx, DMC0_LDQS, DMC0_LDQS, DMC0_UDQS, DMC0_UDQS, PA_xx, PB_xx, PC_xx, SYS_BMODEx, SYS_HWRST, SYS_FAULT, 

SYS_NMI, TWI0_SCL, TWI0_SDA, and SYS_EXTWAKE.

44ns

tHSYS

System Inputs Hold After JTG_TCK High

tTRSTW

JTG_TRST Pulse Width (Measured in JTG_TCK Cycles)2

2 50 MHz maximum.

44tTCK

Switching Characteristics

tDTDO

JTG_TDO Delay From JTG_TCK Low

16.5

14.5

tDSYS

System Outputs Delay After JTG_TCK Low

3 System outputs = DMC0_Axx, DMC0_BAx, DMC0_CAS, DMC0_CK, DMC0_CK, DMC0_CKE, DMC0_CS0, DMC0_DQxx, DMC0_LDM, DMC0_LDQS, DMC0_LDQS,

DMC0_ODT, DMC0_RAS, DMC0_UDM, DMC0_UDQS, DMC0_UDQS, DMC0_WE, PA_xx, PB_xx, PC_xx, SYS_CLKOUT, SYS_FAULT, SYS_RESOUT, and SYS_NMI.

16.5

tDTMS

TMS Delay After TCK High in SWD Mode

3.5

16.5

3.5

14.5

Figure 26. JTAG Port Timing

JTG_TCK

JTG_TMS

JTG_TDI

JTG_TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS

tTCK

tSTAP

tHTAP

tDTDO

tSSYS

tHSYS

tDSYS

ADSP-BF705BBCZ-4 Datasheet(PDF) 78 Page - Analog Devices

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