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ADSP-BF705BBCZ-4 Datasheet(PDF) 87 Page - Analog Devices |
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ADSP-BF705BBCZ-4 Datasheet(HTML) 87 Page - Analog Devices |
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87 / 116 page ![]() Rev. A | Page 87 of 116 | September 2015 ADSP-BF700/701/702/703/704/705/706/707 Serial Peripheral Interface (SPI) Port—Slave Timing Table 55 and Figure 32 describe serial peripheral interface (SPI) port slave operations. Note that: • In dual mode data transmit, the SPI_MOSI signal is also an output. • In quad mode data transmit, the SPI_MOSI, SPI_D2, and SPI_D3 signals are also outputs. • In dual mode data receive, the SPI_MISO signal is also an input. • In quad mode data receive, the SPI_MISO, SPI_D2, and SPI_D3 signals are also inputs. • In SPI slave mode, the SPI clock is supplied externally and is called fSPICLKEXT: Table 55. Serial Peripheral Interface (SPI) Port—Slave Timing Parameter VDD_EXT 1.8V Nominal VDD_EXT 3.3V Nominal MinMax MinMax Unit Timing Requirements tSPICHS SPI_CLK High Period 1 1 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPI_CLK. For the external SPI_CLK ideal maximum frequency see the fSPICLKTEXT specification in Table 18 on Page 52 of Clock Related Operating Conditions. (0.5 × tSPICLKEXT) – 1.5 (0.5 × tSPICLKEXT) – 1.5 ns tSPICLS SPI_CLK Low Period1 (0.5 × tSPICLKEXT) – 1.5 (0.5 × tSPICLKEXT) – 1.5 ns tSPICLK SPI_CLK Period 1 tSPICLKEXT – 1.5 tSPICLKEXT – 1.5 ns tHDS Last SPI_CLK Edge to SPI_SS Not Asserted (NonSPIHP) 55 ns tHDS Last SPI_CLK Edge to SPI_SS Not Asserted (Using SPIHP) 1.5 × tSCLK0 1.5 × tSCLK0 ns tSPITDS Sequential Transfer Delay (NonSPIHP) 0.5 × tSPICLK – 1.5 0.5 × tSPICLK – 1.5 ns tSPITDS Sequential Transfer Delay (Using SPIHP) 3 × tSCLK0 3 × tSCLK0 ns tSDSCI SPI_SS Assertion to First SPI_CLK Edge 11.5 11.5 ns tSSPID Data Input Valid to SPI_CLK Edge (Data Input Setup) 1.5 1 ns tHSPID SPI_CLK Sampling Edge to Data Input Invalid 3.3 3 ns Switching Characteristics tDSOE SPI_SS Assertion to Data Out Active 0 17.5 0 14.5 ns tDSDHI SPI_SS Deassertion to Data High Impedance 0 13 0 11.5 ns tDDSPID SPI_CLK Edge to Data Out Valid (Data Out Delay) 17.5 14.5 ns tHDSPID SPI_CLK Edge to Data Out Invalid (Data Out Hold) 2.5 2.5 ns tSPICLKEXT 1 fSPICLKEXT ----------------------------- = |
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