ADSP-BF705BBCZ-4 datasheet(12/116 Pages) AD

12 / 116 page

Rev. A

Page 12 of 116

September 2015

ADSP-BF700/701/702/703/704/705/706/707

The CAN controller offers the following features:

• 32 mailboxes (8 receive only, 8 transmit only, 16 configu-

rable for receive or transmit)

• Dedicated acceptance masks for each mailbox

• Additional data filtering on first two bytes

• Support for both the standard (11-bit) and extended

(29-bit) identifier (ID) message formats

• Support for remote frames

• Active or passive network support

• CAN wake-up from hibernation mode (lowest static power

consumption mode)

• Interrupts, including: TX complete, RX complete, error

and global

An additional crystal is not required to supply the CAN clock, as

the CAN clock is derived from a system clock through a pro-

grammable divider.

USB 2.0 On-the-Go Dual-Role Device Controller

The USB 2.0 on-the-go (OTG) dual-role device controller pro-

vides a low-cost connectivity solution for the growing adoption

of this bus standard in industrial applications, as well as con-

sumer mobile devices such as cell phones, digital still cameras,

and MP3 players. The USB 2.0 controller allows these devices to

transfer data using a point-to-point USB connection without

the need for a PC host. The module can operate in a traditional

USB peripheral-only mode as well as the host mode presented

in the OTG supplement to the USB 2.0 specification.

The USB clock is provided through a dedicated external crystal

or crystal oscillator.

The USB OTG dual-role device controller includes a phase

locked loop with programmable multipliers to generate the nec-

essary internal clocking frequency for USB.

Housekeeping ADC (HADC)

The HADC provides a general-purpose, multichannel succes-

sive approximation analog-to-digital converter. It supports the

following features:

• 12-bit ADC core (10-bit accuracy) with built-in sample and

hold

• 4 single-ended input channels

• Throughput rates up to 1 MSPS

• Single external reference with analog inputs between 0 V

and 3.3 V

• Selectable ADC clock frequency including the ability to

program a prescaler

• Adaptable conversion type: allows single or continuous

conversion with option of autoscan

• Auto sequencing capability with up to 4 autoconversions in

a single session. Each conversion can be programmed to

select any input channel.

• Four data registers (individually addressable) to store con-

version values

System Crossbars (SCB)

The system crossbars (SCB) are the fundamental building

blocks of a switch-fabric style for (on-chip) system bus inter-

connection. The SCBs connect system bus masters to system

bus slaves, providing concurrent data transfer between multiple

bus masters and multiple bus slaves. A hierarchical model—

built from multiple SCBs—provides a power and area efficient

system interconnect, which satisfies the performance and flexi-

bility requirements of a specific system.

The SCBs provide the following features:

• Highly efficient, pipelined bus transfer protocol for sus-

tained throughput

• Full-duplex bus operation for flexibility and reduced

latency

• Concurrent bus transfer support to allow multiple bus

masters to access bus slaves simultaneously

• Protection model (privileged/secure) support for selective

bus interconnect protection

POWER AND CLOCK MANAGEMENT

The processor provides three operating modes, each with a dif-

ferent performance/power profile. Control of clocking to each

of the processor peripherals also reduces power consumption.

See Table 5 for a summary of the power settings for each mode.

System Crystal Oscillator and USB Crystal Oscillator

The processor can be clocked by an external crystal (see

Figure 4), a sine wave input, or a buffered, shaped clock derived

from an external clock oscillator. If an external clock is used, it

should be a TTL compatible signal and must not be halted,

changed, or operated below the specified frequency during nor-

mal operation. This signal is connected to the SYS_CLKIN pin

of the processor. When an external clock is used, the SYS_XTAL

pin must be left unconnected. Alternatively, because the proces-

sor includes an on-chip oscillator circuit, an external crystal

may be used.

For fundamental frequency operation, use the circuit shown in

Figure 4. A parallel-resonant, fundamental frequency, micro-

processor grade crystal is connected across the SYS_CLKIN and

SYS_XTAL pins. The on-chip resistance between SYS_CLKIN

and the SYS_XTAL pin is in the 500 kΩ range. Further parallel

resistors are typically not recommended.

The two capacitors and the series resistor shown in Figure 4

fine-tune phase and amplitude of the sine frequency. The capac-

itor and resistor values shown in Figure 4 are typical values

only. The capacitor values are dependent upon the load capaci-

tance recommendations of the crystal manufacturer and the

PCB physical layout. The resistor value depends on the drive

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