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ADSP-BF705BBCZ-4 Datasheet(PDF) 19 Page - Analog Devices |
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ADSP-BF705BBCZ-4 Datasheet(HTML) 19 Page - Analog Devices |
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19 / 116 page ![]() Rev. A | Page 19 of 116 | September 2015 ADSP-BF700/701/702/703/704/705/706/707 HADC_VREFN Input Ground Reference for ADC. Connect to an external voltage reference that meets data sheet specifications. HADC_VREFP Input External Reference for ADC. Connect to an external voltage reference that meets data sheet specifications. MSI_CD Input Card Detect. Connects to a pull-up resistor and to the card detect output of an SD socket. MSI_CLK Output Clock. The clock signal applied to the connected device from the MSI. MSI_CMD I/O Command. Used to send commands to and receive responses from the connected device. MSI_Dn I/O Data n. Bidirectional data bus. MSI_INT Input eSDIO Interrupt Input. Used only for eSDIO. Connects to an eSDIO card's interrupt output. An interrupt may be sampled even when the MSI clock to the card is switched off. Px_nn I/O Position n. General purpose input/output. See the GP Ports chapter of the HRM for programming information. RTC_CLKIN Input Crystal input/external oscillator connection. Connect to an external clock source or crystal. RTC_XTAL Output Crystal output. Drives an external crystal. Must be left unconnected if an external clock is driving RTC_CLKIN. SMC_ABEn Output Byte Enable n. Indicate whether the lower or upper byte of a memory is being accessed. When an asynchronous write is made to the upper byte of a 16-bit memory, SMC_ABE1b=0 and SMC_ABE0b=1. When an asynchronous write is made to the lower byte of a 16-bit memory, SMC_ABE1b=1 and SMC_ ABE0b=0. SMC_AMSn Output Memory Select n. Typically connects to the chip select of a memory device. SMC_AOE Output Output Enable. Asserts at the beginning of the setup period of a read access. SMC_ARDY Input Asynchronous Ready. Flow control signal used by memory devices to indicate to the SMC when further transactions may proceed. SMC_ARE Output Read Enable. Asserts at the beginning of a read access. SMC_AWE Output Write Enable. Asserts for the duration of a write access period. SMC_Ann Output Address n. Address bus. SMC_Dnn I/O Data n. Bidirectional data bus. SPI_CLK I/O Clock. Input in slave mode, output in master mode. SPI_D2 I/O Data 2. Used to transfer serial data in Quad mode. Open-drain when ODM mode is enabled. SPI_D3 I/O Data 3. Used to transfer serial data in Quad mode. Open-drain when ODM mode is enabled. SPI_MISO I/O Master In, Slave Out. Used to transfer serial data. Operates in the same direction as SPI_MOSI in Dual and Quad modes. Open-drain when ODM mode is enabled. SPI_MOSI I/O Master Out, Slave In. Used to transfer serial data. Operates in the same direction as SPI_MISO in Dual and Quad modes. Open-drain when ODM mode is enabled. SPI_RDY I/O Ready. Optional flow signal. Output in slave mode, input in master mode. SPI_SELn Output Slave Select Output n. Used in Master mode to enable the desired slave. SPI_SS Input Slave Select Input. Slave mode - Acts as the slave select input. Master mode- Optionally serves as an error detection input for the SPI when there are multiple masters. SPT_ACLK I/O Channel A Clock. Data and Frame Sync are driven/sampled with respect to this clock. This signal can be either internally or externally generated. SPT_AD0 I/O Channel A Data 0. Primary bidirectional data I/O. This signal can be configured as an output to transmit serial data, or as an input to receive serial data. SPT_AD1 I/O Channel A Data 1. Secondary bidirectional data I/O. This signal can be configured as an output to transmit serial data, or as an input to receive serial data. SPT_AFS I/O Channel A Frame Sync. The frame sync pulse initiates shifting of serial data. This signal is either generated internally or externally. SPT_ATDV Output Channel A Transmit Data Valid. This signal is optional and only active when SPORT is configured in multichannel transmit mode. It is asserted during enabled slots. Table 6. ADSP-BF70x Detailed Signal Descriptions (Continued) Port Name Direction Description |
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