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ADSP-BF705BBCZ-4 Datasheet(PDF) 97 Page - Analog Devices

Part # ADSP-BF705BBCZ-4
Description  Instruction set compatible with previous Blackfin products
PDF  116 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADSP-BF705BBCZ-4 Datasheet(HTML) 97 Page - Analog Devices

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Rev. A
|
Page 97 of 116
|
September 2015
ADSP-BF700/701/702/703/704/705/706/707
Table 61. Enhanced Parallel Peripheral Interface—External Clock
VDD_EXT
1.8V Nominal
VDD_EXT
3.3V Nominal
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tPCLKW
EPPI_CLK Width
1
(0.5 × tPCLKEXT) – 1
(0.5 × tPCLKEXT) – 1
ns
tPCLK
EPPI_CLK Period1
tPCLKEXT – 1
tPCLKEXT – 1
ns
tSFSPE
External FS Setup Before EPPI_CLK
1.5
1
ns
tHFSPE
External FS Hold After EPPI_CLK
3.3
3
ns
tSDRPE
Receive Data Setup Before EPPI_CLK
1
1
ns
tHDRPE
Receive Data Hold After EPPI_CLK
3
3
ns
Switching Characteristics
tDFSPE
Internal FS Delay After EPPI_CLK
17.5
14.5
ns
tHOFSPE
Internal FS Hold After EPPI_CLK
2.5
2.5
ns
tDDTPE
Transmit Data Delay After EPPI_CLK
17.5
14.5
ns
tHDTPE
Transmit Data Hold After EPPI_CLK
2.5
2.5
ns
1 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external EPPI_CLK. For the external
EPPI_CLK ideal maximum frequency, see the fPCLKEXT specification in Table 18 on Page 52 in Clock Related Operating Conditions.
Figure 45. PPI External Clock GP Receive Mode with Internal Frame Sync Timing
Figure 46. PPI External Clock GP Transmit Mode with Internal Frame Sync Timing
tHDRPE
tSDRPE
tHOFSPE
FRAME SYNC
DRIVEN
DATA
SAMPLED
tDFSPE
tPCLK
tPCLKW
EPPI_Dx
EPPI_FS1/2
EPPI_CLK
POLC[1:0] = 10
POLC[1:0] = 01
tHOFSPE
FRAME SYNC
DRIVEN
DATA
DRIVEN
tDFSPE
tDDTPE
tHDTPE
tPCLK
tPCLKW
DATA
DRIVEN
EPPI_Dx
EPPI_FS1/2
EPPI_CLK
POLC[1:0] = 11
POLC[1:0] = 00



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