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ADSP-BF705BBCZ-4 Datasheet(PDF) 73 Page - Analog Devices |
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ADSP-BF705BBCZ-4 Datasheet(HTML) 73 Page - Analog Devices |
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73 / 116 page  Rev. A | Page 73 of 116 | September 2015 ADSP-BF700/701/702/703/704/705/706/707 Mobile DDR SDRAM Clock and Control Cycle Timing Table 42 and Figure 20 show mobile DDR SDRAM clock and control cycle timing, related to the dynamic memory controller (DMC). Table 42. Mobile DDR SDRAM Clock and Control Cycle Timing, VDD_DMC Nominal 1.8 V 200 MHz Parameter Min Max Unit Switching Characteristics tCK Clock Cycle Time (CL = 2 Not Supported) 5 ns tCH Minimum Clock Pulse Width 0.45 0.55 tCK tCL Maximum Clock Pulse Width 0.45 0.55 tCK tIS Control/Address Setup Relative to DMC0_CK Rise 1.5 ns tIH Control/Address Hold Relative to DMC0_CK Rise 1.5 ns Figure 20. Mobile DDR SDRAM Clock and Control Cycle Timing NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE. ADDRESS = DMC0_A00-13, AND DMC0_BA0-2. DMC0_CK ADDRESS CONTROL tIS tIH tCK tCH tCL DMC0_CK |
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