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ADSP-BF705BBCZ-4 Datasheet(PDF) 79 Page - Analog Devices |
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ADSP-BF705BBCZ-4 Datasheet(HTML) 79 Page - Analog Devices |
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79 / 116 page  Rev. A | Page 79 of 116 | September 2015 ADSP-BF700/701/702/703/704/705/706/707 Serial Ports To determine whether serial port (SPORT) communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) serial clock (SPT_CLK) width. In Figure 27 either the rising edge or the falling edge of SPT_CLK (external or internal) can be used as the active sampling edge. When externally generated the SPORT clock is called fSPTCLKEXT: When internally generated, the programmed SPORT clock (fSPTCLKPROG) frequency in MHz is set by the following equation where CLKDIV is a field in the SPORT_DIV register that can be set from 0 to 65,535: Table 49. Serial Ports—External Clock VDD_EXT 1.8V Nominal VDD_EXT 3.3V Nominal Parameter Min Max Min Max Unit Timing Requirements tSFSE Frame Sync Setup Before SPT_CLK (Externally Generated Frame Sync in Either Transmit or Receive Mode)1 1 Referenced to sample edge. 1.5 1 ns tHFSE Frame Sync Hold After SPT_CLK (Externally Generated Frame Sync in Either Transmit or Receive Mode) 1 33 ns tSDRE Receive Data Setup Before Receive SPT_CLK 1 1.5 1 ns tHDRE Receive Data Hold After SPT_CLK 1 33 ns tSCLKW SPT_CLK Width2 2 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPT_CLK. For the external SPT_CLK ideal maximum frequency, see the fSPTCLKEXT specification in Table 18 on Page 52 in Clock Related Operating Conditions. (0.5 × tSPTCLKEXT) – 1 (0.5 × tSPTCLKEXT) – 1 ns tSPTCLKE SPT_CLK Period2 tSPTCLKEXT – 1 tSPTCLKEXT – 1 ns Switching Characteristics tDFSE Frame Sync Delay After SPT_CLK (Internally Generated Frame Sync in Either Transmit or Receive Mode) 3 3 Referenced to drive edge. 18 15 ns tHOFSE Frame Sync Hold After SPT_CLK (Internally Generated Frame Sync in Either Transmit or Receive Mode)3 2.5 2.5 ns tDDTE Transmit Data Delay After Transmit SPT_CLK 3 18 15 ns tHDTE Transmit Data Hold After Transmit SPT_CLK 3 2.5 2.5 ns tSPTCLKEXT 1 fSPTCLKEXT ------------------------------- = fSPTCLKPROG fSCLK0 CLKDIV 1 + ------------------------------------- = tSPTCLKPROG 1 fSPTCLKPROG ----------------------------------- = |
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