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ADSP-BF705BBCZ-4 Datasheet(PDF) 22 Page - Analog Devices |
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ADSP-BF705BBCZ-4 Datasheet(HTML) 22 Page - Analog Devices |
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22 / 116 page  Rev. A | Page 22 of 116 | September 2015 ADSP-BF700/701/702/703/704/705/706/707 184-BALL CSP_BGA SIGNAL DESCRIPTIONS The processor’s pin definitions are shown in Table 7. The col- umns in this table provide the following information: • Signal Name: The Signal Name column in the table includes the signal name for every pin and (where applica- ble) the GPIO multiplexed pin function for every pin. • Description: The Description column in the table provides a verbose (descriptive) name for the signal. • General-Purpose Port: The Port column in the table shows whether or not the signal is multiplexed with other signals on a general-purpose I/O port pin. • Pin Name: The Pin Name column in the table identifies the name of the package pin (at power on reset) on which the signal is located (if a single function pin) or is multiplexed (if a general-purpose I/O pin). Table 7. ADSP-BF70x 184-Ball CSP_BGA Signal Descriptions Signal Name Description Port Pin Name CAN0_RX CAN0 Receive C PC_02 CAN0_TX CAN0 Transmit C PC_03 CAN1_RX CAN1 Receive A PA_12 CAN1_TX CAN1 Transmit A PA_13 CNT0_DG CNT0 Count Down and Gate A PA_07 CNT0_UD CNT0 Count Up and Direction A PA_15 CNT0_ZM CNT0 Count Zero Marker A PA_13 DMC0_A00 DMC0 Address 0 Not Muxed DMC0_A00 DMC0_A01 DMC0 Address 1 Not Muxed DMC0_A01 DMC0_A02 DMC0 Address 2 Not Muxed DMC0_A02 DMC0_A03 DMC0 Address 3 Not Muxed DMC0_A03 DMC0_A04 DMC0 Address 4 Not Muxed DMC0_A04 DMC0_A05 DMC0 Address 5 Not Muxed DMC0_A05 DMC0_A06 DMC0 Address 6 Not Muxed DMC0_A06 DMC0_A07 DMC0 Address 7 Not Muxed DMC0_A07 DMC0_A08 DMC0 Address 8 Not Muxed DMC0_A08 DMC0_A09 DMC0 Address 9 Not Muxed DMC0_A09 DMC0_A10 DMC0 Address 10 Not Muxed DMC0_A10 DMC0_A11 DMC0 Address 11 Not Muxed DMC0_A11 DMC0_A12 DMC0 Address 12 Not Muxed DMC0_A12 DMC0_A13 DMC0 Address 13 Not Muxed DMC0_A13 DMC0_BA0 DMC0 Bank Address Input 0 Not Muxed DMC0_BA0 DMC0_BA1 DMC0 Bank Address Input 1 Not Muxed DMC0_BA1 DMC0_BA2 DMC0 Bank Address Input 2 Not Muxed DMC0_BA2 DMC0_CAS DMC0 Column Address Strobe Not Muxed DMC0_CAS DMC0_CK DMC0 Clock Not Muxed DMC0_CK DMC0_CKE DMC0 Clock enable Not Muxed DMC0_CKE DMC0_CK DMC0 Clock (complement) Not Muxed DMC0_CK DMC0_CS0 DMC0 Chip Select 0 Not Muxed DMC0_CS0 DMC0_DQ00 DMC0 Data 0 Not Muxed DMC0_DQ00 DMC0_DQ01 DMC0 Data 1 Not Muxed DMC0_DQ01 DMC0_DQ02 DMC0 Data 2 Not Muxed DMC0_DQ02 DMC0_DQ03 DMC0 Data 3 Not Muxed DMC0_DQ03 DMC0_DQ04 DMC0 Data 4 Not Muxed DMC0_DQ04 DMC0_DQ05 DMC0 Data 5 Not Muxed DMC0_DQ05 DMC0_DQ06 DMC0 Data 6 Not Muxed DMC0_DQ06 |
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