ADSP-BF705BBCZ-4 datasheet(14/116 Pages) AD

14 / 116 page

Rev. A

Page 14 of 116

September 2015

ADSP-BF700/701/702/703/704/705/706/707

Power Management

As shown in Table 4, the processor supports multiple power

domains, which maximizes flexibility while maintaining com-

pliance with industry standards and conventions. There are no

sequencing requirements for the various power domains, but all

domains must be powered according to the appropriate Specifi-

cations table for processor operating conditions; even if the

feature/peripheral is not used.

The dynamic power management feature of the processor

allows the processor’s core clock frequency (fCCLK) to be dynam-

ically controlled.

The power dissipated by a processor is largely a function of its

clock frequency and the square of the operating voltage. For

example, reducing the clock frequency by 25% results in a 25%

reduction in dynamic power dissipation.

See Table 5 for a summary of the power settings for each mode.

Full-On Operating Mode—Maximum Performance

In the full-on mode, the PLL is enabled and is not bypassed,

providing capability for maximum operational frequency. This

is the power-up default execution state in which maximum per-

formance can be achieved. The processor core and all enabled

peripherals run at full speed.

Deep Sleep Operating Mode—Maximum Dynamic Power

Savings

The deep sleep mode maximizes dynamic power savings by dis-

abling the clocks to the processor core and to all synchronous

peripherals. Asynchronous peripherals may still be running but

cannot access internal resources or external memory.

Hibernate State—Maximum Static Power Savings

The hibernate state maximizes static power savings by disabling

the voltage and clocks to the processor core and to all of the

peripherals. This setting signals the external voltage regulator

supplying the VDD_INT pins to shut off using the SYS_

EXTWAKE signal, which provides the lowest static power

dissipation.

Any critical information stored internally (for example, mem-

ory contents, register contents, and other information) must be

written to a nonvolatile storage device (or self-refreshed

DRAM) prior to removing power if the processor state is to be

preserved.

Because the VDD_EXT pins can still be supplied in this mode, all of

the external pins three-state, unless otherwise specified. This

allows other devices that may be connected to the processor to

still have power applied without drawing unwanted current.

Reset Control Unit

Reset is the initial state of the whole processor or the core and is

the result of a hardware- or software-triggered event. In this

state, all control registers are set to their default values and func-

tional units are idle. Exiting a full system reset starts with the

core being ready to boot.

The reset control unit (RCU) controls how all the functional

units enter and exit reset. Differences in functional require-

ments and clocking constraints define how reset signals are

generated. Programs must guarantee that none of the reset

functions puts the system into an undefined state or causes

resources to stall. This is particularly important when the core is

reset (programs must ensure that there is no pending system

activity involving the core when it is being reset).

From a system perspective, reset is defined by both the reset tar-

get and the reset source described as follows in the following list.

Table 3. Clock Dividers

Clock Source

Divider (if Available on



SYS_CLKOUT)

CCLK (Core Clock)

By 16

SYSCLK (System Clock)

By 8

SCLK0 (System Clock, All Periph-

erals not Covered by SCLK1)

Not available on SYS_CLKOUT

SCLK1 (System Clock for Crypto

Engines and MDMA)

By 8

DCLK (LPDDR/DDR2 Clock)

By 8

OCLK (Output Clock)

Programmable

CLKBUF

None, direct from SYS_CLKIN

Table 4. Power Domains

Power Domain

VDD Range

All Internal Logic

VDD_INT

DDR2/LPDDR

VDD_DMC

USB

VDD_USB

OTP Memory

VDD_OTP

HADC

VDD_HADC

RTC

VDD_RTC

All Other I/O (Includes SYS, JTAG, and Ports Pins)

VDD_EXT

Table 5. Power Settings

Mode/State PLL

PLL



Bypassed fCCLK

fSYSCLK,

fDCLK,

fSCLK0,

fSCLK1

Core



Power

Full On

Enabled

Enabled Enabled

Deep Sleep

Disabled —

Disabled Disabled

Hibernate

Disabled —

Disabled Disabled

Off

ADSP-BF705BBCZ-4 Datasheet(PDF) 14 Page - Analog Devices

ADSP-BF705BBCZ-4 Datasheet(HTML) 14 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL