ADSP-BF705BBCZ-4 datasheet(9/116 Pages) AD

9 / 116 page

Rev. A

Page 9 of 116

September 2015

ADSP-BF700/701/702/703/704/705/706/707

system event or fault if enabled. ECC protection is fully trans-

parent to the user, even if L2 memory is read or written by 8-bit

or 16-bit entities.

CRC-Protected Memories

While parity bit and ECC protection mainly protect against ran-

dom soft errors in L1 and L2 memory cells, the CRC engines can

be used to protect against systematic errors (pointer errors) and

static content (instruction code) of L1, L2, and even L3 memo-

ries (DDR2, LPDDR). The processor features two CRC engines

which are embedded in the memory-to-memory DMA

controllers. CRC checksums can be calculated or compared on

the fly during memory transfers, or one or multiple memory

regions can be continuously scrubbed by a single DMA work

unit as per DMA descriptor chain instructions. The CRC engine

also protects data loaded during the boot process.

Memory Protection

The Blackfin+ core features a memory protection concept,

which grants data and/or instruction accesses to enabled mem-

ory regions only. A supervisor mode vs. user mode

programming model supports dynamically varying access

rights. Increased flexibility in memory page size options sup-

ports a simple method of static memory partitioning.

System Protection

The system protection unit (SPU) guards against accidental or

unwanted access to the MMR space of a peripheral by providing

a write-protection mechanism. The user is able to choose and

configure the peripherals that are protected as well as configure

which ones of the four system MMR masters (core, memory

DMA, the SPI host port, and Coresight debug) the peripherals

are guarded against.

The SPU is also part of the security infrastructure. Along with

providing write-protection functionality, the SPU is employed

to define which resources in the system are secure or non-secure

and to block access to secure resources from non-secure

masters.

Synonymously, the system memory protection unit (SMPU)

provides memory protection against read and/or write transac-

tions to defined regions of memory. There are two SMPU units

in the ADSP-BF70x processors. One is for the L2 memory and

the other is for the external DDR memory.

The SMPU is also part of the security infrastructure. It allows

the user to not only protect against arbitrary read and/or write

transactions, but it also allows regions of memory to be defined

as secure and prevent non-secure masters from accessing those

memory regions.

Watchpoint Protection

The primary purpose of watchpoints and hardware breakpoints

is to serve emulator needs. When enabled, they signal an emula-

tor event whenever user-defined system resources are accessed

or the core executes from user-defined addresses. Watchpoint

events can be configured such that they signal the events to the

fault management unit of the SEC.

Watchdog

The on-chip software watchdog timer can supervise the

Blackfin+ core.

Bandwidth Monitor

Memory-to-memory DMA channels are equipped with a band-

width monitor mechanism. They can signal a system event or

fault when transactions tend to starve because system buses are

fully loaded with higher-priority traffic.

Signal Watchdogs

The eight general-purpose timers feature modes to monitor off-

chip signals. The watchdog period mode monitors whether

external signals toggle with a period within an expected range.

The watchdog width mode monitors whether the pulse widths

of external signals are within an expected range. Both modes

help to detect undesired toggling (or lack thereof) of 

system-level signals.

Up/Down Count Mismatch Detection

The GP counter can monitor external signal pairs, such as

request/grant strobes. If the edge count mismatch exceeds the

expected range, the GP counter can flag this to the processor or

to the fault management unit of the SEC.

Fault Management

The fault management unit is part of the system event controller

(SEC). Any system event, whether a dual-bit uncorrectable ECC

error, or any peripheral status interrupt, can be defined as being

a fault. Additionally, the system events can be defined as an

interrupt to the core. If defined as such, the SEC forwards the

event to the fault management unit, which may automatically

reset the entire device for reboot, or simply toggle the 

SYS_FAULT output pin to signal off-chip hardware. Optionally,

the fault management unit can delay the action taken through a

keyed sequence, to provide a final chance for the Blackfin+ core

to resolve the issue and to prevent the fault action from being

taken.

ADDITIONAL PROCESSOR PERIPHERALS

The processor contains a rich set of peripherals connected to the

core through several high-bandwidth buses, providing flexibility

in system configuration as well as excellent overall system per-

formance (see the block diagram on Page 1). The processor

contains high-speed serial and parallel ports, an interrupt con-

troller for flexible management of interrupts from the on-chip

peripherals or external sources, and power management control

functions to tailor the performance and power characteristics of

the processor and system to many application scenarios.

The following sections describe additional peripherals that were

not previously described.

Timers

The processor includes several timers which are described in the

following sections.

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