ADSP-BF705BBCZ-4 datasheet(20/116 Pages) AD

20 / 116 page

Rev. A

Page 20 of 116

September 2015

ADSP-BF700/701/702/703/704/705/706/707

SPT_BCLK

I/O

Channel B Clock. Data and Frame Sync are driven/sampled with respect to this clock. This signal can

be either internally or externally generated.

SPT_BD0

I/O

Channel B Data 0. Primary bidirectional data I/O. This signal can be configured as an output to

transmit serial data, or as an input to receive serial data.

SPT_BD1

I/O

Channel B Data 1. Secondary bidirectional data I/O. This signal can be configured as an output to

transmit serial data, or as an input to receive serial data.

SPT_BFS

I/O

Channel B Frame Sync. The frame sync pulse initiates shifting of serial data. This signal is either

generated internally or externally.

SPT_BTDV

Output

Channel B Transmit Data Valid. This signal is optional and only active when SPORT is configured in

multi-channel transmit mode. It is asserted during enabled slots.

SYS_BMODEn

Input

Boot Mode Control n. Selects the boot mode of the processor.

SYS_CLKIN

Input

Clock/Crystal Input. Connect to an external clock source or crystal.

SYS_CLKOUT

Output

Processor Clock Output. Outputs internal clocks. Clocks may be divided down. See the CGU chapter

of the HRM for more details.

SYS_EXTWAKE

Output

External Wake Control. Drives low during hibernate and high all other times. Typically connected to

the enable input of the voltage regulator controlling the VDD_INT supply.

SYS_FAULT

I/O

Active-Low Fault Output. Indicates internal faults or senses external faults depending on the

operating mode.

SYS_HWRST

Input

Processor Hardware Reset Control. Resets the device when asserted.

SYS_NMI

Input

Non-maskable Interrupt. See the processor hardware and programming references for more details.

SYS_RESOUT

Output

Reset Output. Indicates that the device is in the reset or hibernate state.

SYS_WAKEn

Input

Power Saving Mode Wakeup n. Wake-up source input for deep sleep and/or hibernate mode.

SYS_XTAL

Output

Crystal Output. Drives an external crystal. Must be left unconnected if an external clock is driving

CLKIN.

JTG_SWCLK

I/O

Serial Wire Clock. Clocks data into and out of the target during debug.

JTG_SWDIO

I/O

Serial Wire DIO. Sends and receives serial data to and from the target during debug.

JTG_SWO

Output

Serial Wire Out. Provides trace data to the emulator.

JTG_TCK

Input

JTAG Clock. JTAG test access port clock.

JTG_TDI

Input

JTAG Serial Data In. JTAG test access port data input.

JTG_TDO

Output

JTAG Serial Data Out. JTAG test access port data output.

JTG_TMS

Input

JTAG Mode Select. JTAG test access port mode select.

JTG_TRST

Input

JTAG Reset. JTAG test access port reset.

TM_ACIn

Input

Alternate Capture Input n. Provides an additional input for WIDCAP, WATCHDOG, and PININT modes.

TM_ACLKn

Input

Alternate Clock n. Provides an additional time base for use by an individual timer.

TM_CLK

Input

Clock. Provides an additional global time base for use by all the GP timers.

TM_TMRn

I/O

Timer n. The main input/output signal for each timer.

TRACE_CLK

Output

Trace Clock. Clock output.

TRACE_Dnn

Output

Trace Data n. Unidirectional data bus.

TWI_SCL

I/O

Serial Clock. Clock output when master, clock input when slave.

TWI_SDA

I/O

Serial Data. Receives or transmits data.

UART_CTS

Input

Clear to Send. Flow control signal.

UART_RTS

Output

Request to Send. Flow control signal.

UART_RX

Input

Receive. Receive input. Typically connects to a transceiver that meets the electrical requirements of

the device being communicated with.

UART_TX

Output

Transmit. Transmit output. Typically connects to a transceiver that meets the electrical requirements

of the device being communicated with.

USB_CLKIN

Input

Clock/Crystal Input. This clock input is multiplied by a PLL to form the USB clock. See data sheet

specifications for frequency/tolerance information.

Table 6. ADSP-BF70x Detailed Signal Descriptions (Continued)

Port Name

Direction

Description

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